Open-loop valley regulation for supply voltage modulation in power amplifier circuits

US11870396B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11870396-B2
Application numberUS-202117522865-A
CountryUS
Kind codeB2
Filing dateNov 9, 2021
Priority dateJun 6, 2018
Publication dateJan 9, 2024
Grant dateJan 9, 2024

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.

First claim

Opening claim text (preview).

What is claimed is: 1. A power amplifier system comprising: a supply modulator circuit to generate a supply voltage at a supply output based at least on a valley level input; a digital to analog converter configured to receive a digital amplitude signal and to convert the digital amplitude signal to an analog amplitude signal; a power amplifier circuit coupled with the supply output of the supply modulator circuit to receive the supply voltage, having a gain input node to receive the analog amplitude signal, and configured to generate a signal output according to the supply voltage and to one of a plurality of gain settings indicated by the analog amplitude signal; and a valley compensator having a lookup table coupled with the valley level input of the supply modulator circuit and configured to output a compensation signal to the valley level input responsive to receiving the digital amplitude signal, such that the compensation signal indicates one of a plurality of compensation values selected based on a present gain setting of the plurality of gain settings indicated by the digital amplitude signal, wherein each compensation value is stored by the lookup table in association with a respective gain setting one of the plurality of gain settings, and outputting each compensation value to the valley level input directs the supply modulator circuit to output the supply voltage at a respective compensated supply voltage level calibrated, so that applying the respective compensated supply voltage level and the respective gain setting to the power amplifier circuit generates the signal output to have an output valley level substantially at a predetermined target valley level. 2. The power amplifier system of claim 1 , wherein each of the plurality of compensation values designates the respective compensated supply voltage level corresponding thereto. 3. The power amplifier system of claim 1 , wherein: the supply modulator circuit further has a reference voltage input to receive a reference voltage level; and each of the plurality of compensation values designates a difference voltage, such that the reference voltage level less the difference voltage is the respective compensated supply voltage level. 4. The power amplifier system of claim 1 , wherein: each of the plurality of compensation values designates a digital code corresponding to the respective compensated supply voltage level; and the supply modulator circuit is configured to generate the supply voltage at the respective compensated supply voltage level responsive to receiving the digital code at the valley level input. 5. The power amplifier system of claim 1 , further comprising: a second digital to analog converter configured to receive the compensation signal as a digital compensation signal from the valley compensator, to convert the digital compensation signal to an analog compensation signal, and to provide the analog compensation signal to the valley level input of the supply modulator circuit. 6. The power amplifier system of claim 1 , wherein: the respective compensated supply voltage level for each of the plurality of compensation values is calibrated, so that the power amplifier circuit generates the signal output to have an output valley level substantially at a same predetermined target valley level across all of the plurality of gain settings. 7. The power amplifier system of claim 1 , further comprising: a calibration subsystem comprising: a valley detector circuit having a detection input coupled with the signal output of the power amplifier circuit and configured to generate a detection signal as a function of the detection input, such that the detection signal indicates a present output valley level of an amplitude envelope of the signal output of the power amplifier circuit; and a calibration engine coupled with the valley detector circuit and the lookup table and configured, for each gain setting of the plurality of gain settings, to compute a respective one of the plurality of compensation values based on the present output valley level indicated by the detection signal for the gain setting, and to store the respective one of the plurality of compensation values in the lookup table in association with the gain setting. 8. The power amplifier system of claim 7 , wherein: the calibration subsystem further comprises: a comparator circuit to generate a comparator output based on comparing the detection signal with a valley reference signal that corresponds to the predetermined target valley level; and the calibration engine is coupled with the valley detector via the comparator circuit and configured, for each gain setting, to compute the respective one of the plurality of compensation values by: iteratively directing the supply modulator to generate each of a plurality of candidate compensated supply voltage levels at the gain setting while monitoring the comparator output until the comparator output indicates, at one of the candidate compensated supply voltage levels, that the present output valley level is substantially at the predetermined target valley level; and outputting the respective one of the plurality of compensation values for the gain setting based on the one of the candidate compensated supply voltage levels. 9. The power amplifier system of claim 7 , wherein: the calibration subsystem further comprises: a selective coupling configured to couple the calibration subsystem with at least the power amplifier circuit during a calibration phase, and to decouple the calibration subsystem from at least the power amplifier circuit during an operating phase. 10. A method for valley compensation in a power amplifier system, the method comprising: monitoring a digital amplitude signal to detect a present gain setting of a plurality of gain settings, the digital amplitude signal being converted by a digital to analog converter to an analog amplitude signal, the analog amplitude signal used to amplitude modulate a signal output of a power amplifier circuit, the power amplifier circuit generating the signal output according to a supply voltage and to the present gain setting as indicated by the digital amplitude signal; identifying a present compensation value as associated with the present gain setting, the present compensation value being one of a plurality of compensation values, each stored by a lookup table in association with a respective gain setting of the plurality of gain settings, and each corresponding to a respective compensated supply voltage level that is calibrated so that setting the supply voltage to the respective compensated supply voltage level when the present gain setting is set to the respective gain setting causes an output valley level of the signal output generated by the power amplifier circuit to be substantially at a predetermined target valley level; generating a compensation signal based on the present compensation value; and outputting the compensation signal to a supply modulator circuit to generate the supply voltage at the respective compensated supply voltage level corresponding to the present compensation value. 11. The method of claim 10 , wherein each of the plurality of compensation values designates the respective compensated supply voltage level corresponding thereto. 12. The method of claim 10 , wherein: each of the plurality of compensation values designates a difference voltage, such that a reference voltage level less the difference voltage is the respective compensated supply voltage level. 13. The method of claim 10 , wherein: each of the plurality of compensation values designates a digital code cor

Assignees

Inventors

Classifications

  • H03F1/0233Primary

    by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

  • Indicating direction of current; Indicating polarity of voltage · CPC title

  • in AC or DC supplies (G01R19/16519 and G01R19/16528 take precedence) · CPC title

  • adapted for measuring in circuits having distributed constants · CPC title

  • Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature · CPC title

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What does patent US11870396B2 cover?
Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can det…
Who is the assignee on this patent?
Shenzhen Goodix Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H03F1/0233. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 09 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).