Methods and apparatus to reduce variations for on-off keying transmissions

Patent metadata

Field	Value
Publication number	US-11863360-B2
Application number	US-202217584099-A
Country	US
Kind code	B2
Filing date	Jan 25, 2022
Priority date	Jan 25, 2022
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.

First claim

What is claimed is:

1. An apparatus comprising:
an on-off keying (OOK) modulator including:
a first transistor including a first control terminal;
a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal;
a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal;
a fourth transistor including a fourth control terminal, the fourth control terminal coupled to the second current terminal; and
a fifth transistor including a fifth control terminal, the fifth control terminal coupled to the fourth current terminal.

2. The apparatus of claim 1 , wherein the apparatus further includes a level shifting circuit including a resistor coupled in parallel to a sixth transistor, the sixth transistor coupled to the third transistor and configured to short the resistor as a result of being enabled.

3. The apparatus of claim 1 , wherein the OOK modulator is coupled to an oscillator, the oscillator is configured to control a transistor to generate a modulated carrier signal as a result of controlling the first transistor based on a digital input signal.

4. The apparatus of claim 1 , wherein the first transistor is an N-channel metal-oxide-semiconductor field-effect transistor including the first control terminal as a gate terminal.

5. The apparatus of claim 1 , wherein the second transistor is a N-channel metal-oxide-semiconductor field-effect transistor including the second control terminal as a gate terminal, the first current terminal as a source terminal, and the second current terminal as a drain terminal.

6. The apparatus of claim 1 , wherein the third transistor is a N-channel metal-oxide-semiconductor field-effect transistor including the third control terminal as a gate terminal, the third current terminal as a drain terminal, and the fourth current terminal as a source terminal.

7. The apparatus of claim 1 , wherein the fourth transistor is configured to generate a bias voltage to be applied to the first control terminal as a result of enabling the second transistor.

8. The apparatus of claim 1 , wherein the fifth transistor is configured to generate a bias voltage to be applied to the first control terminal as a result of enabling the third transistor.

9. A system comprising:
a level shifting circuit configured to generate a digital output based on a digital input, wherein voltage level of the digital output is shifter from voltage level of the digital input; and
an on-off keying (OOK) modulator coupled to the level shifting circuit, circuit and comprising:
a first transistor having a first terminal and a second terminal, wherein the first terminal is coupled to a first bias voltage;
a second transistor having a third terminal and a fourth terminal, wherein the third terminal is coupled to a second bias voltage; and
a third transistor having a control terminal coupled to the second terminal of the first transistor and the fourth terminal of the second transistor, wherein
the OOK modulator configured to:
turn on the first transistor to apply the first bias voltage to the control terminal of the third transistor in response to a first state of the digital output;
turn on the second transistor to apply the second bias voltage to the control terminal of the third transistor in response to a second state of the digital output which is opposite to the first state;
generate a current through the third transistor based on the voltage applied to the control terminal of the third transistor; and
generate a modulated carrier signal based on an output of an oscillator and the current through the third transistor.

10. The system of claim 9 , wherein the system further includes a current mirror including an output, the output is coupled to the digital input.

11. The system of claim 9 , wherein that the level shifting circuit includes a first switch and a second switch, in which the first switch is configured to be enabled by the first state of the digital output, and the second switch is configured to be enabled by the second state of the digital output.

12. The system of claim 9 , wherein the OOK modulator is further configured to disable the third transistor as a result of coupling the second bias voltage to the control terminal.

13. The system of claim 9 , wherein the OOK modulator is further configured to provide the first bias voltage to the control terminal of the third transistor based on a bias current, the first bias voltage is configured to enable the third transistor.

14. The system of claim 9 , wherein the OOK modulator is further configured to provide the second bias voltage to the control terminal of the third transistor based on a bias current, the second bias voltage is set at voltage magnitude smaller than a threshold voltage of the third transistor but higher than a ground level and configured to disable the third transistor.

15. A method comprising:
providing a first bias voltage at a control terminal of a transistor through a first transistor when a digital output is in a first state;
providing a second bias voltage at the control terminal of the transistor through a second transistor when the digital output is in a second state;
generating a current through the transistor based on voltage at the control terminal of the transistor; and
generating a modulated carrier signal based on an output of an oscillator and the current through the transistor.

16. The method of claim 15 , wherein the voltage coupled to the control terminal of the transistor is of a range of a first bias voltage to a second bias voltage, the control terminal enables the transistor as a result of a voltage in the range being coupled to the control terminal.

17. The method of claim 15 , wherein the transistor is a primary transistor, the first bias voltage is determined based on a current flowing through a secondary transistor, the secondary transistor is configured to generate the first bias voltage coupled to the control terminal.

18. The method of claim 15 , wherein the transistor is a primary transistor, the second bias voltage is determined based on a current flowing through a secondary transistor, the secondary transistor is configured to generate the second bias voltage coupled to the control terminal.

19. The method of claim 15 , wherein the current generated by the transistor is configured to be controlled by a differential output of the oscillator.

Assignees

• Texas Instruments Inc

Inventors

• Shrivastava Kumar Anurag
• Akhtar Siraj
• Sankaran Swaminathan
• Kamath Anant Shankar

Classifications

• H04L27/04 Primary

  Modulator circuits; Transmitter circuits · CPC title

• H03C1/06

  Modifications of modulator to reduce distortion, e.g. by feedback, and clearly applicable to more than one type of modulator · CPC title

• H03C1/36

  by means of semiconductor device having at least three electrodes (H03C1/34, H03C1/50, H03C1/52, H03C1/62 take precedence) · CPC title

• H03D7/1458 Primary

  Double balanced arrangements, i.e. where both input signals are differential · CPC title

• H03C2200/0025

  Gilbert multipliers · CPC title