Semiconductor storage device
US-2016189801-A1 · Jun 30, 2016 · US
Data storage device and operating method thereof
US10943639B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10943639-B2 |
| Application number | US-202016733140-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 2, 2020 |
| Priority date | Dec 18, 2017 |
| Publication date | Mar 9, 2021 |
| Grant date | Mar 9, 2021 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory device comprising: a plurality of memory blocks each including a plurality of pages; and a control logic configured to determine a memory block to perform a refresh operation in response to a refresh scan command from a host and to control the memory block to perform the refresh operation to recover data of the memory block, wherein the memory block has a read count exceeding a first predetermined threshold number. 2. The memory device of claim 1 , wherein the refresh operation includes a read reclaim operation. 3. The memory device of claim 1 , wherein the refresh operation includes a wear leveling operation. 4. The memory device of claim 1 , wherein the memory block has a program-erase count exceeding a second predetermined threshold number. 5. The memory device of claim 1 , wherein the control logic controls to copy the data to one of the plurality of memory blocks. 6. A memory device comprising: a plurality of memory blocks each including a plurality of pages; and a control logic configured to perform a refresh operation to recover data of a selected memory block among the plurality of memory blocks without a request of a host device, wherein the selected memory block has a program-erase count exceeding a first predetermined threshold number. 7. The memory device of claim 6 , wherein the refresh operation includes a read reclaim operation. 8. The memory device of claim 6 , wherein the refresh operation includes a wear leveling operation. 9. The memory device of claim 6 , wherein the selected memory block has a program-erase count exceeding a second predetermined threshold number. 10. The memory device of claim 6 , wherein the control logic controls to copy the data to one of the plurality of memory blocks. 11. A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block, wherein the memory block has a read count exceeding a first predetermined threshold number. 12. The storage device of claim 11 , wherein the refresh operation includes a read reclaim operation. 13. The storage device of claim 11 , wherein the refresh operation includes a wear leveling operation. 14. The storage device of claim 11 , wherein the memory block has a program-erase count exceeding a second predetermined threshold number. 15. The storage device of claim 11 , wherein the device controller controls to copy the data to one of the plurality of memory blocks.
Assignees
Inventors
Classifications
Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification · CPC title
- G11C16/10Primary
Programming or data input circuits · CPC title
Identification of the type of error · CPC title
by changing the state or mode of one or more devices · CPC title
- G06F3/0619Primary
in relation to data integrity, e.g. data losses, bit errors · CPC title
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Frequently asked questions
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- What does patent US10943639B2 cover?
- A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/10. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 09 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).