Semiconductor storage device having nonvolatile semiconductor memory

US9299455B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9299455-B2
Application numberUS-201213500057-A
CountryUS
Kind codeB2
Filing dateMar 6, 2012
Priority dateMar 6, 2012
Publication dateMar 29, 2016
Grant dateMar 29, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor storage device, comprising: a nonvolatile semiconductor memory comprising a plurality of storage areas; and a controller, which is coupled to the nonvolatile semiconductor memory, wherein the controller is configured to manage storage area state information on a basis of each storage area, including at least one of information related to elapsed time after data is written to the storage area and information related to cumulative erase number of the storage area; wherein the controller is configured to manage read parameter information including one or more read parameters relevant to at least one of elapsed time after data programming to the storage areas and cumulative erase number of the storage areas; wherein the controller is configured to specify a first read parameter corresponding to a first storage area of the plurality of storage areas, based on the storage area state information corresponding to the first storage area and the read parameter information; wherein the controller is configured to read data from the first storage area by using the first read parameter; wherein the storage area state information is configured to further include information related to an ambient temperature of each of the storage areas; wherein the read parameter information is configured to manage the one or more read parameters for the storage areas at a standard temperature; and wherein the controller is configured to convert the elapsed time after the data is written to the storage area at the ambient temperature into an adjusted elapsed time at the standard temperature, and wherein the controller is configured to specify the first read parameter by using the adjusted elapsed time. 2. A semiconductor storage device, comprising: a nonvolatile semiconductor memory comprising a plurality of storage areas; and a controller, which is coupled to the nonvolatile semiconductor memory, wherein the controller is configured to manage storage area state information on a basis of each storage area, including at least one of information related to elapsed time after data is written to the storage area and information related to cumulative erase number of the storage area; wherein the controller is configured to manage read parameter information including one or more read parameters relevant to at least one of elapsed time after data programming to the storage areas and cumulative erase number of the storage areas; wherein the controller is configured to specify a first read parameter corresponding to a first storage area of the plurality of storage areas, based on the storage area state information corresponding to the first storage area and the read parameter information; and wherein the controller is configured to read data from the first storage area by using the first read parameter, wherein each of the plurality of storage areas is configured with at least one of one or more cells in a chip of the nonvolatile semiconductor memory, and wherein each of the one or more read parameters is configured to include at least one of the following (x) through (z): (x) a voltage value of a read voltage supplied to a target word line of the one or more cells corresponding to a read target storage area (y) a read time for waiting for a measurement of the voltage value of the read voltage; and (z) a voltage value of a pass voltage supplied to other word lines of the one or more cells corresponding to a read target storage area and information for identifying the other word lines. 3. The semiconductor storage device according to claim 2 , wherein. the controller is configured to determine whether or not the data read from the first storage area is normal; wherein in a case where the result of the determination is negative, the controller is configured to search for a second read parameter for acquiring normal data from the first storage area; and wherein the controller is configured to register the second read parameter instead of the first read parameter in the read parameter information. 4. The semiconductor storage device according to claim 2 , wherein the controller is configured to specify the first read parameter upon receiving a read request to the first storage area from an external device. 5. The semiconductor storage device according to claim 4 , wherein the controller is configured to manage information related to a degree of deterioration corresponding to each of the plurality of the storage areas in the storage area management information, in which the degree of deterioration is calculated by the elapsed time after programming data and the read parameters, wherein when the controller receives a data write request from an external device, the controller is configured to preferentially allocate a storage area based on the information related to the degree of deterioration. 6. The semiconductor storage device according to claim 2 , wherein the controller is configured to read the data from the first storage area by supplying the read voltage included in the first read parameter to corresponding word line of the one or more cells of the nonvolatile semiconductor memory. 7. A semiconductor storage device, comprising: a nonvolatile semiconductor memory comprising a plurality of storage areas; and a controller, which is coupled to the nonvolatile semiconductor memory, wherein the controller is configured to manage storage area state information on a basis of each storage area, including at least one of information related to elapsed time after data is written to the storage area and information related to cumulative erase number of the storage area; wherein the controller is configured to manage read parameter information including one or more read parameters relevant to at least one of elapsed time after data programming to the storage areas and cumulative erase number of the storage areas; wherein the controller is configured to specify a first read parameter corresponding to a first storage area of the plurality of storage areas, based on the storage area state information corresponding to the first storage area and the read parameter information; and wherein the controller is configured to read data from the first storage area by using the first read parameter, wherein the controller is configured to specify the first read parameter at a predetermined time on a regular basis and to hold the specified first read parameter in storage area management information, unrelated to receiving a read request to the first storage area from an external device. 8. The semiconductor storage device according to claim 7 , wherein the controller is configured to determine, based on the value of the first read parameter, whether or not it is necessary to execute a refresh for moving the data from the first storage area data to another storage area; and wherein in a case where the result of the determination is affirmative, the controller is configured to execute the refresh with respect to the first storage area. 9. The semiconductor storage device according to claim 8 , wherein the controller is configured to store a threshold related to a read voltage included in the read parameters, the controller is configured to compare a first read voltage included in the first read parameter to the threshold, and in a case where the first read voltage is less than the threshold, the controller is configured to execute the refresh to the first storage area. 10. The semiconductor storage device according to claim 7 , wherein the controller is configured to read the data from the first storage area by using the first read parameter in order to determine whether a number of erro

Assignees

Inventors

Classifications

  • Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • Configuration or reconfiguration of storage systems · CPC title

  • G06F3/0616Primary

    in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

  • Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

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What does patent US9299455B2 cover?
A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when re…
Who is the assignee on this patent?
Suzuki Akifumi, Tsunehiro Takashi, Hitachi Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0616. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).