Semiconductor storage device

Patent metadata

Field	Value
Publication number	US-2016189801-A1
Application number	US-201615059477-A
Country	US
Kind code	A1
Filing date	Mar 3, 2016
Priority date	Sep 4, 2013
Publication date	Jun 30, 2016
Grant date	—

Abstract

A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.

First claim

1 . A semiconductor storage device comprising:
a memory cell array that has a plurality of memory cells, a plurality of word lines connected to at least some memory cells of the plurality of memory cells, a plurality of bit lines connected to at least some memory cells of the plurality of memory cells, and a plurality of blocks including a group of at least some memory cells of the plurality of memory cells; a defect information storage block that is at least one of the plurality of blocks and stores defect information in the memory cell array; a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block; a second defect detection circuitry that, when it is determined by the first defect detection circuitry that there is the defect, changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block; and a defect determination circuitry that, when it is determined by the second defect detection circuitry that there is the defect, determines the defect information storage block as a defective block.

2 . The semiconductor storage device according to claim 1 ,
wherein the first and second defect detection circuitries determine whether there is the defect in the defect information storage block, whenever the semiconductor storage device executes a power-on read operation.

3 . The semiconductor storage device according to claim 1 ,
wherein at least one of the first and second defect detection circuitries determines that there is the defect, when the number of inversions of storage data of at least some memory cells on a specific word line in the defect information storage block is more than a predetermined value.

4 . The semiconductor storage device according to claim 1 ,
wherein at least one of the first and second defect detection circuitries writes specific data given to a specific bit line in the defect information storage block to the memory cells connected to the specific bit line, compares data read from the memory cells and the specific data, and determines whether there is the defect.

5 . The semiconductor storage device according to claim 1 ,
wherein at least one of the first and second defect detection circuitries writes complementary data to at least some memory cells on a specific word line in the defect information storage block, reads the complementary data, compares the complementary data, and determines whether there is the defect.

6 . The semiconductor storage device according to claim 1 , further comprising:
a third defect detection circuitry that, when it is determined that there is no defect, by at least one of the first and second defect detection circuitries, writes complementary data to at least a part of the defect information storage block, reads the written complementary data, compares the complementary data, and determines whether there is the defect in the defect information storage block.

7 . The semiconductor storage device according to claim 1 ,
wherein the defect information storage block associates address information represented by quotients obtained by dividing addresses to designate individual blocks or individual columns obtained by dividing the memory cell array in a block unit or a column unit by n (n is an integer of 2 or more) and n-bit data in which defect information of each of n blocks or columns is set as one bit and stores an association result.

8 . The semiconductor storage device according to claim 7 ,
wherein the defect information storage block associates the address information, inversion data of the address information, the n-bit data, and inversion data of the n-bit data and stores an association result.

9 . The semiconductor storage device according to claim 7 , further comprising:
a defect information holding circuitry that reads the defect information stored in the defect information storage block and holds the defect information; and an address conversion circuitry that converts the addresses to have access to the defect information storage block into addresses to have access to the defect information holding circuitry, wherein the defect information holding circuitry has a plurality of latch circuits that store the defect information of the block unit or the column unit stored in the defect information storage block individually in association with the addresses converted by the address conversion circuitry.

10 . A semiconductor storage device comprising:
a memory cell array that has a plurality of memory cells, a plurality of word lines connected to at least some memory cells of the plurality of memory cells, a plurality of bit lines connected to at least some memory cells of the plurality of memory cells, and a plurality of blocks including a group of at least some memory cells of the plurality of memory cells; a defect information storage block that is at least one of the plurality of blocks and stores defect information in the memory cell array; a spare storage block that stores the same defect information as the defect information storage block; a first defect detection circuitry that determines whether there is a defect in the defect information storage block; a data erasure circuitry that, when it is detected by the first defect detection circuitry that there is the defect in the defect information storage block, erases storage data of all memory cells in the defect information storage block; a temporary holding circuitry that reads the defect information stored in the spare storage block and holds the defect information temporarily; and a defect information write circuitry that writes the defect information held in the temporary holding circuitry to the defect information storage block after erasure by the data erasure circuitry.

11 . The semiconductor storage device according to claim 10 , further comprising:
a second defect detection circuitry that, when it is detected that there is the defect in the defect information storage block, detects whether there is the defect in the spare storage block, wherein the data erasure circuitry erases the storage data of the memory cells in the defect information storage block, when it is detected by the first defect detection circuitry that there is the defect in the defect information storage block and it is detected by the second defect detection circuitry that there is no defect in the spare storage block.

12 . The semiconductor storage device according to claim 10 ,
wherein the first and second defect detection circuitries determine whether there is the defect, whenever the semiconductor storage device executes a power-on read operation.

13 . The semiconductor storage device according to claim 10 ,
wherein the first defect detection circuitry detects whether there is the defect in the defect information storage block, on the basis of a read result of data of the memory cells on a specific word line in the defect information storage block, and the defect information write circuitry writes the defect information held in the temporary holding circuitry to the memory cells on the word lines other than the specific word line where the defect has been detected by the first defect detection circuitry, in the defect information storage block.

14 . The semiconductor storage device according to claim 10 , further comprising:
a defect determination circ

Assignees

• Toshiba Kk

Inventors

• Yamaguchi Kouichirou
• Miakashi Makoto
• Shiga Hitoshi
• Shibata Noboru

Classifications

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title