Shift register unit, gate drive circuit and method of driving the same

Patent metadata

Field	Value
Publication number	US-10943552-B2
Application number	US-201715768309-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Jan 22, 2017
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

First claim

What is claimed is:

1. A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises:
a control circuit configured to output a control signal,
at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output a scan signal to a gate line,
wherein the control circuit comprises:
a first pull-up control circuit coupled to a first signal input terminal, a signal output terminal of the control circuit, and a first voltage terminal, the first pull-up control circuit configured to output a signal of the first voltage terminal to the signal output terminal of the control circuit under control of a signal of the first signal input terminal;
a first pull-down control circuit coupled to a first clock signal terminal, a second clock signal terminal, the first signal input terminal, a second voltage terminal, a fourth voltage terminal, and a first pull-down node, the first pull-down control circuit configured to control a voltage level of the first pull-down node under control of signals of the first clock signal terminal, the second clock signal terminal and the first signal input terminal;
a second pull-down control circuit coupled to the first clock signal terminal, the second clock signal terminal, the first signal input terminal, a third voltage terminal, the fourth voltage terminal, and a second pull-down node, the second pull-down control circuit configured to control a voltage level of the second pull-down node under control of signals of the first clock signal terminal, the second clock signal terminal and the first signal input terminal;
a first pull-down circuit coupled to the first pull-down node, the signal output terminal of the control circuit, and the fourth voltage terminal, the first pull-down circuit configured to pull a voltage at the signal output terminal of the control circuit down to the voltage of the fourth voltage terminal under control of a voltage level of the first pull-down node;
a second pull-down circuit coupled to the second pull-down node, the signal output terminal of the control circuit, and the fourth voltage terminal, the second pull-down circuit configured to pull the voltage of the signal output terminal of the control circuit down to the voltage of the fourth voltage terminal under control of a voltage level of the second pull-down node; and
a reset circuit coupled to a second signal input terminal, the first voltage terminal, and the second pull-down node, the reset circuit being configured to output a voltage of the first voltage terminal to the second pull-down node under control of a signal of the second signal input terminal;
wherein each of the at least two buffer circuits comprises:
a second pull-up control circuit coupled to a pull-up control node, the second voltage terminal, the third voltage terminal, and the signal output terminal of the control circuit, the second pull-up control circuit configured to turn on and output a signal of the signal output terminal of the control circuit to the pull-up control node under control of a signal of the second voltage terminal and a signal of the third voltage terminal;
a pull-up circuit coupled to the pull-up control node, a third clock signal terminal, and a signal output terminal of the buffer circuit, the pull-up circuit being configured to output a signal of the third clock signal terminal to the signal output terminal of the buffer circuit under control of a voltage of the pull-up control node;
a third pull-down circuit coupled to the first pull-down node, the fourth voltage terminal, and the signal output terminal of the buffer circuit, the third pull-down circuit being configured to pull a voltage of the signal output terminal of the buffer circuit down to the voltage of the fourth voltage terminal under control of a voltage level of the first pull-down node; and
a fourth pull-down circuit is coupled to the second pull-down node, the fourth voltage terminal, and the signal output terminal of the buffer circuit, the fourth pull-down circuit configured to pull the voltage of the signal output terminal of the buffer circuit down to the voltage of the fourth voltage terminal under control of a voltage level of the second pull-down node.

2. The shift register unit according to claim 1 , wherein the first pull-up control circuit comprises:
a first transistor, wherein a gate of the first transistor is coupled to the first signal input terminal, a first electrode of the first transistor is coupled to the first voltage terminal, and a second electrode thereof is coupled to the signal output terminal of the control circuit.

3. The shift register unit according to claim 1 , wherein the first pull-down control circuit comprises: a second transistor, a third transistor, and a fourth transistor;
wherein a gate of the second transistor is coupled to the first clock signal terminal, a first electrode of the second transistor is coupled to the second voltage terminal, and a second electrode thereof is coupled to a first electrode of the third transistor;
wherein a gate of the third transistor is coupled to the second clock signal terminal, and a second electrode of the third transistor is coupled to the first pull-down node; and
wherein a gate of the fourth transistor is coupled to the first signal input terminal, a first electrode of the fourth transistor is coupled to the fourth voltage terminal, and a second electrode thereof is coupled to the first pull-down node.

4. The shift register unit according to claim 1 , wherein the second pull-down control circuit comprises a fifth transistor, a sixth transistor, and a seventh transistor;
wherein a gate of the fifth transistor is coupled to the first clock signal terminal, a first electrode of the fifth transistor is coupled to the third voltage terminal, and a second electrode thereof is coupled to a first electrode of the sixth transistor;
wherein a gate of the sixth transistor is coupled to the second clock signal terminal, and a second electrode of the sixth transistor is coupled to the second pull-down node; and
wherein a gate of the seventh transistor is coupled to the first signal input terminal, a first electrode of the seventh transistor is coupled to the fourth voltage terminal, and a second electrode thereof is coupled to the second pull-down node.

5. The shift register unit according to claim 1 , wherein the first pull-down circuit comprises:
an eighth transistor, wherein a gate of the eighth transistor is coupled to the first pull-down node, a first electrode of the eighth transistor is coupled to the fourth voltage terminal, and a second electrode thereof is coupled to the signal output terminal of the control circuit.

6. The shift register unit according to claim 1 , wherein the second pull-down circuit comprises:
a ninth transistor, wherein a gate of the ninth transistor is coupled to the second pull-down node, a first electrode of the ninth transistor is coupled to the fourth voltage terminal, and a first second electrode thereof is coupled to the signal output terminal of the control circuit.

7. The shift register unit according to claim 1 , wherein the reset circuit comprises:
a tenth transistor, where a gate of the tenth transistor is coupled to the second signal input terminal, a first electrode of the tenth transistor is coupled to the first voltage terminal, and a second electrode thereof is coupled to the second pull-down node.

8. The shift register unit according to claim 1 , wherein the second pull-up control circuit comprises an eleventh transistor and a twelfth transistor;
wherein a gate of the eleventh transistor is coupled to the third voltage terminal, a first electrode of the eleventh transistor

Assignees

• Boe Technology Group Co Ltd

Inventors

• Kim Jiha
• Han Seungwoo
• Shang Guangliang
• Zheng Haoliang
• Yao Xing
• Wang Zhichong
• Han Mingfu
• Yuan Lijun
• Im Yunsik
• Lv Jing
• Dong Xue

Classifications

• G09G2340/0414

  Vertical resolution change · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G2340/0407

  Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title