Integrated ultralong time constant time measurement device and fabrication process

Patent metadata

Field	Value
Publication number	US-10937746-B2
Application number	US-201916549000-A
Country	US
Kind code	B2
Filing date	Aug 23, 2019
Priority date	Aug 31, 2018
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

First claim

The invention claimed is:

1. An ultralong time constant time measurement device, comprising:
a plurality of elementary capacitive elements connected in a series;
a capacitive storage element that is connected to one end of the series connected plurality of elementary capacitive elements and is configured to be charged;
wherein the series connected plurality of elementary capacitive elements is configured to discharge the charged capacitive storage element and to deliver, to at least one node of the series connected plurality of elementary capacitive elements, a physical quantity that is representative of the discharging of the capacitive storage element and a duration that has elapsed between a start of an operation of discharging the capacitive storage element and a time at which the physical quantity is delivered;
wherein each elementary capacitive element comprises:
a stack of a first conductive region, a dielectric layer having a thickness that allows charge to flow by direct tunneling effect and a second conductive region,
wherein the first conductive region is housed in a trench extending from a front face of a semiconductor substrate into the semiconductor substrate, and
wherein the dielectric layer rests on the front face of the semiconductor substrate and the second conductive region rests on the dielectric layer.

2. The device according to claim 1 , wherein said stack is located facing a portion of a width of said trench housing the first conductive region on said front face.

3. The device according to claim 1 , wherein pairs of elementary capacitive elements in the series connection are connected, alternately, by the second conductive region that is common to two consecutive elementary capacitive elements and by the first conductive region that is common to two consecutive elementary capacitive elements.

4. The device according to claim 1 , wherein the semiconductor substrate comprises an electrical isolation region extending vertically into the semiconductor substrate from the first face, wherein said trench housing the first conductive region of each elementary capacitive element passes through the electrical isolation region.

5. The device according to claim 1 , further comprising:
a semiconductor well that is housed in the semiconductor substrate where said series connected plurality of elementary capacitive elements are located;
a first contact and a second contact which are electrically connected by an electrical path through the semiconductor well comprising a section that is located between a bottom of the trench and a bottom of the semiconductor well; and
a detection circuit configured to detect an electrical discontinuity in the semiconductor well between the first contact and the second contact.

6. The device according to claim 1 , further comprising a comparator having an input coupled to said at least one node of the series connected plurality of elementary capacitive elements, said comparator configured to compare the physical quantity at said at least one node to a threshold.

7. The device according to claim 6 , wherein an output from the comparator is a binary value indicative of said duration.

8. The device according to claim 1 , wherein a pair of elementary capacitive elements in the series connection is connected by one second conductive region that is common to the elementary capacitive elements of said pair.

9. The device according to claim 1 , wherein a pair of elementary capacitive elements in the series connection is connected by one first conductive region that is common to the elementary capacitive elements of said pair.

10. The device according to claim 1 , wherein said at least one node of the series connected plurality of elementary capacitive elements comprises a first node and a second node, and further comprising:
a first comparator having an input coupled to said first node, said first comparator configured to compare the physical quantity at said first node to a first threshold; and
a second comparator having an input coupled to said second node, said second comparator configured to compare the physical quantity at said second node to a second threshold.

11. The device according to claim 10 , wherein outputs from the first and second comparator provide a binary word indicative of said duration.

Assignees

• St Microelectronics Rousset

Inventors

• Marzaki Abderrezak
• Fornara Pascal

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D84/813 Primary

  Combinations of field-effect devices and capacitor only · CPC title

• H10D86/85

  characterised by only passive components · CPC title