Circuit and method for detecting a fault attack

Patent metadata

Field	Value
Publication number	US-8963574-B2
Application number	US-201113095432-A
Country	US
Kind code	B2
Filing date	Apr 27, 2011
Priority date	May 3, 2010
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.

First claim

What is claimed is:

1. A device for detecting a fault attack, comprising:
a circuit for detecting an interruption of a power supply; a circuit for comparing a duration of said interruption with a first threshold, the circuit for comparing being coupled to the circuit for detecting; and a counter coupled to the circuit for comparing and configured to count a number of successive interruptions of the power supply having a duration which does not exceed said first threshold, wherein the circuit for detecting comprises, between two terminals of application of a power supply voltage:
a MOS transistor having a source, a drain, and a bulk connected together; and
a capacitor having a first electrode electrically coupled to a gate of said MOS transistor.

2. The device of claim 1 , wherein the counter is automatically reset to zero when the duration of an interruption of the power supply exceeds the first threshold.

3. The device of claim 1 , further comprising an alert device when the counter reaches a second threshold.

4. The device of claim 1 , wherein the circuit for comparing the duration of the interruption with a first threshold comprises a circuit for comparing the voltage across the capacitor with a third threshold.

5. The device of claim 1 , wherein the MOS transistor having its source, its drain, and its bulk connected together comprises a portion forming a gate oxide having a thickness lower than 3 nm.

6. The device of claim 1 , wherein the counter of the number of successive interruptions comprises a set of memory points having their state reset to zero when a duration of an interruption exceeds a first threshold.

7. A chip card comprising the device of claim 1 .

8. A device for detecting a fault attack, comprising:
a circuit for detecting an interruption of a power supply;
a circuit for comparing a duration of said interruption with a first threshold, the circuit for comparing being coupled to the circuit for detecting; and
a counter coupled to the circuit for comparing and configured to count a number of successive interruptions of the power supply having a duration which does not exceed said first threshold, wherein the counter comprises a set of memory points having respective states reset to zero when a duration of an interruption exceeds a first threshold, wherein each memory point comprises:
between first and second terminals of application of a power supply voltage, a first branch comprising a series connection of a first, of a second, and of a third MOS transistor, the second and third MOS transistors having respective gates connected together, and a second branch comprising a series connection of a fourth, of a fifth, and of a sixth MOS transistor, the fifth and sixth MOS transistors having gates that are connected together;
a first capacitor connected between the gate of the first MOS transistor and said second terminal, and a second capacitor connected between a gate of the fourth MOS transistor and said second terminal;
a seventh MOS transistor having a source, a drain, and a substrate terminal connected to the gate of the second MOS transistor and having a gate connected to the gate of the first MOS transistor, and
an eighth MOS transistor having a source, a drain, and a bulk connected to the gate of the fifth MOS transistor and having a gate connected to the gate of the fourth MOS transistor.

9. The device of claim 8 , wherein the seventh MOS transistor and the eighth MOS transistor comprise a portion forming a gate oxide having a thickness smaller than a thickness of gate-oxide-forming portions of the first, second, third, fourth, fifth, and sixth MOS transistors.

10. A method for detecting a fault attack on an electronic circuit, comprising:
detecting an interruption of the circuit power supply;
comparing a duration of the interruption with a first threshold;
incrementing a counter if the duration of the interruption is shorter than said first threshold and resetting to zero said counter if the duration of the interruption is greater than said first threshold; and
comparing a value stored in the counter with a second threshold.

11. The method of claim 10 , further comprising generating of an alert if the value stored in the counter is greater than said second threshold.

12. A static volatile memory cell insensitive to a short interruption of its power supply, comprising:
between a first and a second terminals of application of a power supply voltage, a first branch comprising a series connection of a first, of a second, and of a third MOS transistor, the gates of the second and third MOS transistors being connected together, and a second branch comprising a series connection of a fourth, of a fifth, and of a sixth MOS transistor, the gates of the fifth and sixth MOS transistors being connected together;
a first capacitor connected between the gate of the first MOS transistor and said second terminal, and a second capacitor connected between the gate of the fourth MOS transistor and said second terminal; and
a seventh transistor MOS having its source, its drain, and its bulk connected to the gate of the second MOS transistor and having its gate connected to the gate of the first MOS transistor, and an eighth MOS transistor having its source, its drain, and its bulk connected to the gate of the fifth MOS transistor and having its gate connected to the gate of the fourth MOS transistor.

Assignees

• La Rosa Francesco
• St Microelectronics Rousset

Inventors

• La Rosa Francesco

Classifications

• G06F21/552 Primary

  involving long-term monitoring or reporting · CPC title

• G06F21/554

  involving event detection and direct action · CPC title

• G06F21/77 Primary

  in smart cards · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title