Vertically-constructed, temperature-sensing resistors and methods of making the same

Patent metadata

Field	Value
Publication number	US-10937574-B2
Application number	US-201916576809-A
Country	US
Kind code	B2
Filing date	Sep 20, 2019
Priority date	Nov 13, 2017
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within the semiconductor substrate and including a top contact. A conductive layer located over the semiconductor substrate electrically connects to a subset of the top contacts.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within a semiconductor substrate and including a top contact to a semiconductor resistive region; and
a conductive layer located over the semiconductor substrate and connecting to a subset of the resistor unit cells via corresponding ones of the top contacts.

2. The integrated circuit of claim 1 , wherein the conductive layer includes a bond pad.

3. The integrated circuit of claim 1 , wherein the conductive layer includes a laser-trimmed link.

4. The integrated circuit of claim 1 , wherein each resistor unit cell includes a layer of the semiconductor substrate that has a temperature-dependent resistance.

5. The integrated circuit of claim 1 , wherein each resistor unit cell is electrically connected to a same bottom-side contact, the semiconductor resistive region located between the top contacts and the bottom-side contact.

6. The integrated circuit of claim 1 , wherein each resistor unit cell includes an isolation ring that conductively isolates that resistor unit cell from neighboring resistor unit cells.

7. The integrated circuit of claim 6 , wherein the isolation ring is circular.

8. The integrated circuit of claim 1 , wherein the conductive layer connects the subset of resistor unit cells in parallel.

9. The integrated circuit of claim 1 , wherein a circuit formed by the conductive layer and the subset of resistor unit cells includes a tunnel link between two neighboring unit cells.

10. The integrated circuit of claim 1 , wherein each semiconductor resistive region includes a lightly-doped semiconductor layer between two heavily doped semiconductor layers.

11. A method, comprising:
forming a plurality of resistor unit cells in a semiconductor substrate, the resistor unit cells arranged in an array and each including a corresponding top contact to a semiconductor resistive region; and
forming a conductive layer over the semiconductor substrate, the conductive layer connecting to a subset of the resistor unit cells via corresponding ones of the top contacts.

12. The method of claim 11 , wherein the conductive layer includes a bond pad.

13. The method of claim 11 , further comprising laser trimming the conductive layer.

14. The method of claim 11 , wherein each resistor unit cell includes a layer of the semiconductor substrate that has a temperature-dependent resistance.

15. The method of claim 11 , further comprising forming a bottom-side contact on the semiconductor substrate such that each resistor unit cell is electrically connected to the bottom-side contact.

16. The method of claim 11 , wherein each resistor unit cell includes an isolation ring that conductively isolates that resistor unit cell from neighboring resistor unit cells.

17. The method of claim 16 , wherein the isolation ring is circular.

18. The method of claim 11 , wherein the conductive layer connects the subset of resistor unit cells in parallel.

19. The method of claim 11 , further comprising forming a tunnel link between two neighboring unit cells.

20. The method of claim 11 , wherein each semiconductor resistive region includes a lightly-doped semiconductor layer between two heavily doped semiconductor layers.

21. An integrated circuit, comprising:
a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within a semiconductor substrate and including a top contact; and
a conductive layer located over the semiconductor substrate and connecting to a subset of the resistor unit cells,
wherein a circuit formed by the conductive layer and the subset of resistor unit cells includes a tunnel link between two neighboring unit cells.

22. An integrated circuit, comprising:
a plurality of resistor unit cells arranged in an array within a semiconductor substrate, each resistor unit cell including a semiconductor layer that has a temperature-dependent resistance and a top contact to the semiconductor layer; and
a conductive layer located over the semiconductor substrate and connecting to a subset of the top contacts.

Assignees

• Texas Instruments Inc

Inventors

• Cestra Gregory Keith
• Strachan Andrew

Classifications

• H10D84/209

  of only resistors · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title

• H01C7/008 Primary

  Thermistors (H01C7/02 - H01C7/06 take precedence) · CPC title

• H01C13/02

  Structural combinations of resistors · CPC title

• H01C7/06

  including means to minimise changes in resistance with changes in temperature · CPC title