High density MRAM integration

Patent metadata

Field	Value
Publication number	US-10930703-B2
Application number	US-201816237194-A
Country	US
Kind code	B2
Filing date	Dec 31, 2018
Priority date	Jul 6, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

First claim

What is claimed is:

1. A magnetic memory array, comprising:
a substrate;
a control gate structure formed over the substrate;
a semiconductor pillar structure adjacent to the control gate;
a silicide capping layer formed over and in contact with the semiconductor pillar structure; and
a magnetic element formed over the capping layer;
wherein at least a portion of the semiconductor pillar structure is monocrystalline semiconductor.

2. The magnetic memory array as in claim 1 , wherein the silicide capping layer comprises one or more of CoSi 2 , TiSi 2 , or NiS 2 .

3. The magnetic memory array as in claim 1 , further comprising a silicide seed layer, wherein the semiconductor structure is formed on the silicide seed layer.

4. The magnetic memory array as in claim 3 , wherein the silicide seed layer comprises one or more of TiSi 2 (210) (1.7%), CoSi 2 (1.2%) or NiSi 2 (0.4%).

5. The magnetic memory array as in claim 1 , wherein the semiconductor structure is cylindrical having first and second ends and an outer side that extends between the first and second ends.

6. The magnetic memory array as in claim 5 , wherein the gate control structure further comprises a gate dielectric contacting the outer side of the cylindrical semiconductor structure and an electrically conductive line connected with the gate dielectric.

7. The magnetic memory array as in claim 1 , wherein the memory element is a magnetic tunnel junction element, and wherein the memory element is electrically connected with the semiconductor structure.

8. The magnetic memory array as in claim 1 , wherein the substrate comprises monocrystalline silicon.

9. The magnetic memory array as in claim 1 , further comprising an electrode having one or more textures in contact with the silicide.

10. The magnetic memory array as in claim 1 , wherein the capping layer includes a silicide of one or various ordering degrees.

11. A magnetic memory array, comprising:
a silicide seed layer;
a semiconductor pillar structure formed on the seed layer;
a gate structure connected with the semiconductor structure; and
a magnetic memory element, electrically connected with the semiconductor structure;
wherein at least a portion of the semiconductor pillar structure is monocrystalline.

12. A magnetic memory array as in claim 11 , wherein the gate structure includes a gate dielectric layer at least partially surrounding the monocrystalline semiconductor cylinder and an electrically conductive line contacting the gate dielectric such that the gate dielectric is between the semiconductor structure and the electrically conductive line.

13. The magnetic memory array as in claim 11 , wherein the silicide seed layer comprises one or more of CoSi 2 , TiSi 2 , or NiS 2 .

14. The magnetic memory array as in claim 11 , wherein the magnetic memory element comprises a magnetic tunnel junction element that is formed over the semiconductor structure.

Assignees

• Spin Memory Inc

Inventors

• Kim Kuk-Hwan
• Beery Dafna
• Gajek Marcin
• Tzoufras Michail
• Bozdag Kadriye Deniz
• Ryan Eric Michael
• Araki Satoru
• Walker Andrew J

Classifications

• H10N50/85

  Materials of the active region · CPC title

• G11C11/155

  with cylindrical configuration · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• G11C11/1659

  Cell access · CPC title