Semiconductor integrated circuit device having vertical channel and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016013292-A1
Application number	US-201414518813-A
Country	US
Kind code	A1
Filing date	Oct 20, 2014
Priority date	Jul 9, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. A gate electrode having a lower height than each active line is formed on a sidewall of the active line. A first insulating layer having a height lower than that of the active line and higher than that of the gate electrode is buried between active lines, and a silicide layer is formed on an exposed upper surface and a lateral surface of the active line.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor integrated circuit device, the method comprising:
forming an active line over a semiconductor substrate; forming a gate electrode over a lower sidewall of the active line; forming a first insulating layer between the active line and a neighboring active line to bury the gate electrode, wherein an upper portion of the active line is exposed over the first insulating layer; and forming a silicide layer over an upper surface and a sidewall of the upper portion of the active line.

2 . The method of claim 1 , further comprising:
between the forming of the active line and the forming of the gate electrode, forming a gate insulating layer between the lower sidewall of the active line and the gate electrode.

3 . The method of claim 2 , further comprising:
between the forming of the gate electrode and the forming of the first insulating layer, forming a lightly doped drain (LDD) ion region in the active line exposed by the gate electrode.

4 . The method of claim 3 , further comprising:
between the forming of the first insulating layer and the forming of the silicide layer, forming a drain region in the upper portion of the active line and forming a common source region extending from the semiconductor substrate under the active line to the semiconductor substrate under the neighboring active line, wherein impurity concentrations in the drain region and in the common source region are higher than an impurity concentration in the lightly doped drain (LDD) ion region.

5 . The method of claim 4 , further comprising:
after the forming of the drain region and the common source region, forming a contact ion region in a surface of the drain region, wherein the contact ion region has an impurity concentration higher than the impurity concentration of the drain region.

6 . The method of claim 1 , further comprising:
gap-filling a second insulating layer between the active line and the neighboring active line; forming a mask pattern extending in a direction substantially perpendicular to the active line over the second insulating layer; and forming active pillars by patterning the active line using the mask pattern.

7 . The method of claim 6 , further comprising: after the forming of the active pillars,
gap-filling a third insulating layer between the active pillars; and planarizing the third insulating layer to expose the silicide layer.

8 . The method of claim 1 , further comprising:
forming a lower electrode over the silicide layer; forming a variable resistance layer over the lower electrode; and forming an upper electrode over the variable resistance layer.

9 . A method of manufacturing a semiconductor integrated circuit device, the method comprising:
forming first and second active lines, extending parallel to each other, over a semiconductor substrate, wherein each of the active lines has a first conductivity type; forming a gate electrode over a lower sidewall of the first active line, wherein the gate electrode has a linear shape; gap-filling a first insulating layer between the first and the second active lines, wherein the first insulating layer extends up to a level higher than the gate electrode; forming a drain region in an upper portion of the first active line and forming a source region in the semiconductor substrate under the first active line, wherein each of the drain and the source regions has an impurity having a second conductivity type opposite to the first conductivity type, wherein the upper portion of the first active line is exposed over the gate electrode; forming a silicide layer extending from an upper surface of the drain region to a sidewall of the drain region; gap-filling a second insulating layer over the silicide layer and over the first insulating layer; and etching the first active line using a mask extending in a direction substantially perpendicular to the first active line to form an active pillar, wherein an upper portion of the active pillar is covered by the silicide layer.

10 . The method of claim 9 , further comprising:
between the forming of the first and the second active lines and the forming of the gate electrode, forming a gate insulating layer between the first active line and the gate electrode.

11 . The method of claim 10 , further comprising:
between the forming of the gate electrode and the gap-filling of the first insulating layer, forming a lightly doped drain (LDD) region in the first active line exposed by the gate electrode.

12 . The method of claim 9 , further comprising:
between the forming of the drain region and the forming of the silicide layer, forming a contact ion region along a surface of the drain region, wherein the contact ion region has an impurity having a second conductivity type, wherein the contact ion region has a higher impurity concentration than an impurity concentration of the drain region.

13 . The method of claim 9 , further comprising: after the forming of the active pillar,
forming a lower electrode over the silicide layer; forming a variable resistance layer over the lower electrode; and forming an upper electrode over the variable resistance layer.

14 . A semiconductor integrated circuit device comprising:
an active pillar; a drain region formed in an upper portion of the active pillar; a source region formed in a semiconductor substrate which is provided under the active pillar; a gate electrode formed in a linear form over a lower sidewall of the active pillar; and a silicide layer extending from an upper surface of the drain region to a sidewall of the drain region.

15 . The semiconductor integrated circuit device of claim 14 ,
wherein the gate electrode extends between the drain region and the source region, and wherein the gate electrode is spaced apart from the silicide layer and electrically insulated from the silicide layer.

16 . The semiconductor integrated circuit device of claim 14 , wherein a gate insulating layer is interposed between the gate electrode and the active pillar.

17 . The semiconductor integrated circuit device of claim 14 , further comprising:
a contact ion region formed between the drain region and the silicide layer, wherein the contact ion region has a higher impurity concentration than the drain region.

18 . The semiconductor integrated circuit device of claim 14 , wherein the silicide layer is located at a level higher than the gate electrode.

Assignees

• Sk Hynix Inc

Inventors

• Choi Kang Sik

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/6715

  characterised by the doping profiles, e.g. having lightly-doped source or drain extensions · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title