High density MRAM integration

Patent metadata

Field	Value
Publication number	US-10686009-B2
Application number	US-201816237171-A
Country	US
Kind code	B2
Filing date	Dec 31, 2018
Priority date	Jul 6, 2018
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

First claim

What is claimed is:

1. A magnetic memory array, comprising:
a semiconductor substrate having an n-doped region;
a plurality of gate levels formed over the semiconductor substrate;
a plurality of memory element levels, each memory element level being formed on a gate level;
a pillar structure extending through the plurality of gate levels and plurality of memory element levels, the pillar structure including crystalline silicon surrounded by a gate dielectric in regions of the gate level, and fully silicided silicon having no surrounding gate dielectric in regions of the memory element regions.

2. The magnetic memory array as in claim 1 , wherein the pillar structure further includes a layer of silicide located between the crystalline semiconductor and the fully silicided silicon.

3. The magnetic memory array as in claim 1 , wherein the crystalline silicon comprises one or more of poly-crystalline, micro-crystalline, nano-crystalline or monocrystalline silicon.

4. The magnetic memory array as in claim 1 , wherein the pillar structure extends to the doped region of the semiconductor substrate.

5. The magnetic memory array as in claim 1 , wherein each of the plurality of channel gate levels further includes a layer of electrically conductive material and a layer of dielectric material located at the top and bottom of the electrically conductive material.

6. The magnetic memory array as in claim 1 , wherein each of the plurality of magnetic memory element levels includes at least one magnetic tunnel junction magnetic memory element.

7. The magnetic memory array as in claim 1 , wherein each of the plurality of magnetic memory element levels includes a plurality of magnetic tunnel junction magnetic memory elements.

8. The magnetic memory array as in claim 1 , wherein each of the plurality of magnetic memory element levels includes a plurality of magnetic tunnel junction magnetic memory elements that are connected at one end to one another by a layer of electrically conductive material.

9. The magnetic memory array as in claim 8 , wherein the layer of electrically conductive material comprises TiN.

10. The magnetic memory array as in claim 1 , wherein each of the plurality of magnetic memory element levels further comprises a plurality of magnetic tunnel junction memory elements each having an electrically conductive bit line connected therewith.

11. A method for manufacturing a three-dimensional magnetic memory array, the method comprising:
forming a semiconductor substrate having an n-doped region;
forming a plurality of gate levels and magnetic memory element levels over the semiconductor substrate;
forming an opening in the plurality of gate levels and magnetic memory levels, the opening terminating at the n-doped region of the semiconductor substrate;
forming a gate dielectric layer on a side of the opening, leaving the underlying n-doped region of the substrate uncovered by the gate dielectric layer;
forming crystalline silicon structures surrounded by gate dielectric in the opening in regions of the gate levels and fully silicided silicon structures having no surrounding gate dielectric in regions of the memory element levels.

12. The method as in claim 11 , further comprising forming a silicide layer over each of the crystalline silicon structures.

13. The method as in claim 11 , wherein the silicide layer comprises TiSi 2 .

14. The method as in claim 11 , wherein each of the magnetic memory element levels is formed over a gate level, and wherein each gate level includes a layer of electrically conductive material having a layer of dielectric material formed above and below the gate dielectric.

15. The method as in claim 11 , wherein the formation of fully silicided silicon further comprises: depositing amorphous silicon; depositing Ni; performing a silicidation process; and removing any unreacted Ni.

16. The method as in claim 11 , wherein the formation of fully silicided silicon is performed by low temperature epitaxial silicon growth, Ni deposition, silicidation and removal of unreacted Ni.

Assignees

• Spin Memory Inc

Inventors

• Kim Kuk-Hwan
• Beery Dafna
• Gajek Marcin
• Tzoufras Michail
• Bozdag Kadriye Deniz
• Ryan Eric Michael
• Araki Satoru
• Walker Andrew J

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H10N50/01

  Manufacture or treatment · CPC title