Semiconductor devices with package-level configurability

Patent metadata

Field	Value
Publication number	US-10930645-B2
Application number	US-202016743451-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Nov 13, 2017
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

First claim

We claim:

1. A semiconductor device assembly, comprising:
a substrate;
a die coupled to the substrate, the die including:
a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element,
a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and
a third contact pad electrically coupled to a third circuit on the die including only passive circuit elements;

wherein the substrate includes a substrate contact electrically coupled to both the first contact pad and the second contact pad on the die.

2. The semiconductor device assembly of claim 1 , wherein the first circuit is a driver circuit.

3. The semiconductor device assembly of claim 1 , wherein each of the second circuit and the third circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

4. The semiconductor device assembly of claim 1 , wherein the die is a NAND memory die.

5. The semiconductor device assembly of claim 1 , wherein the substrate contact is electrically disconnected from the third contact pad on the die.

6. The semiconductor device assembly of claim 1 , wherein the substrate contact is electrically coupled to the third contact pad on the die.

7. The semiconductor device assembly of claim 1 , wherein the third contact pad on the die is electrically disconnected from every other circuit on the die other than the third circuit.

8. The semiconductor device assembly of claim 1 , wherein the second contact pad is adjacent the third contact pad.

9. The semiconductor device assembly of claim 1 , wherein the die is a first die, further comprising:
a second die including:
a fourth contact pad electrically coupled to a fourth circuit on the second die including at least a second active circuit element,
a fifth contact pad electrically coupled to a fifth circuit on the second die including only passive circuit elements, and
a sixth contact pad electrically coupled to a sixth circuit on the second die including only passive circuit elements;

wherein the substrate contact is electrically coupled to the fourth contact pad on the second die, and
wherein the fifth contact pad on the second die is electrically disconnected from the substrate contact.

10. The semiconductor device assembly of claim 9 , wherein the first and second dies are identical dies, wherein the first contact pad on the first die corresponds to the fourth contact pad on the second die, and the second contact pad on the first die corresponds to the fifth contact pad on the second die.

11. The semiconductor device assembly of claim 9 , wherein the first and second dies are stacked in a shingled configuration.

12. The semiconductor device assembly of claim 9 , wherein the substrate contact is electrically coupled to the fourth contact pad by a wirebond between the first and fourth contact pads.

13. A method of making a semiconductor device assembly, comprising:
providing a substrate including a substrate contact;
coupling one or more semiconductor dies to the substrate, wherein each of the one or more semiconductor dies includes:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element,
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements, and
a third contact pad electrically coupled to a third circuit on the semiconductor die including only passive circuit elements;

electrically coupling the substrate contact to both the first and second contact pads of a first one of the one or more semiconductor dies.

14. The method of claim 13 , wherein the first circuit of each of the one or more semiconductor dies is a driver circuit.

15. The method of claim 13 , wherein each of the second circuit and the third circuit of each of the one or more semiconductor dies includes one or more capacitors to provide electrostatic discharge (ESD) protection.

16. The method of claim 13 , wherein the one or more semiconductor dies comprise at least one NAND memory die.

17. The method of claim 13 , wherein the one or more semiconductor dies comprise a plurality of semiconductor dies stacked in a shingled configuration.

18. The method of claim 13 , wherein the substrate contact is electrically disconnected from the third contact pad on the first one of the one or more semiconductor dies.

19. The method of claim 13 , further comprising electrically coupling the substrate contact to the third contact pad on the first one of the one or more semiconductor dies.

20. The method of claim 13 , wherein the third contact pad on the first one of the one or more semiconductor dies is electrically disconnected from every other circuit on the first one of the one or more semiconductor dies other than the third circuit.

Assignees

• Micron Technology Inc

Inventors

• Davis James E
• Pusey John B
• Yin Zhiping
• Duesman Kevin G

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/07554

  changes in dispositions · CPC title