MMIO addressing using a translation table

Patent metadata

Field	Value
Publication number	US-10929302-B2
Application number	US-201816003862-A
Country	US
Kind code	B2
Filing date	Jun 8, 2018
Priority date	Jun 8, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

First claim

What is claimed is:

1. A method for processing an instruction by a processor, wherein the processor is operationally connected to one or more buses, wherein the method comprises:
determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses;
determining the address being accessed by the instruction is within the range of MMIO addresses;
translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus,
write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests,
wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address; and
sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation.

2. The method of claim 1 , wherein the buses are PCIe (Peripheral Component Interconnect Express) buses, wherein the device is a PCIe device, and wherein the bus address is a PCIe bus address.

3. The method of claim 1 , wherein the address space comprising the address accessed by the instruction is an absolute partition address space assigned to a first partition of a plurality of partitions operating on a system, each partition of the plurality of partitions having a discrete translation table, wherein the translation table is assigned to the first partition, and wherein the instruction is issued by the first partition.

4. The method of claim 3 , further comprising:
receiving, by the processor, a partition identifier identifying the first partition.

5. The method of claim 3 , wherein the translation table contains translations for each address of the MMIO range, wherein each address of the MMIO range has an assigned access indicator which indicates whether an access to the respective address of the MMIO range is allowed.

6. The method of claim 3 , wherein the translation table only contains translations for addresses of the MMIO range that the first partition is allowed to access.

7. The method of claim 1 , further comprising:
determining, whether the bus address resulting from the translation lies within a range of the bus address space assigned to the bus identified by the bus identifier resulting from the translation.

8. The method of claim 7 , wherein the translation table comprises identifiers identifying an upper limit and a lower limit of the bus address space assigned to the bus identified by the bus identifier resulting from the translation for determining whether the resulting bus address lies within the range defined by the upper and the lower limit.

9. The method of claim 1 , wherein the address being accessed by the instruction comprises a first section encoding an identifier for identifying the bus identifier.

10. The method of claim 9 , wherein the identifier for identifying the bus identifier comprises an entry identifier identifying an entry in the translation table providing the bus identifier.

11. The method of claim 9 , wherein the address comprises a second section encoding the bus address of the bus address space assigned to the device accessible via the bus identified by the first section.

12. The method of claim 1 , wherein the method further comprises:
combining, in response to determining that the address being accessed is the second one of the two addresses, data of the instruction with other data being transmitted to the bus address; and
storing the combined data in the aggregation buffer.

13. The method of claim 1 , wherein the bus identifier comprises one or more of the following for identifying the bus: a node number, a chip number, a bus unit number, and a bus number.

14. The method of claim 1 , wherein the method further comprises:
determining whether write combine is enabled for the addresses of the MMIO range by checking a value of a writing combining enabled bit that is added to the MMIO range.

15. A system for processing an instruction by a processor comprising:
one or more processors, wherein the one or more processors are operationally connected to one or more buses; and
a memory communicatively coupled to the one or more processors,
wherein the memory comprises instructions which, when executed by the one or more processors, cause the one or more processors to perform a method comprising:
determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses;
determining the address being accessed by the instruction is within the range of MMIO addresses;
translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus, and wherein the bus address is distinct from the MMIO addresses,
write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests,
wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address; and
sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation.

16. A computer program product for processing an instruction by a processor, the computer program product comprising a computer readable storage medium having machine executable program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a computer to perform a method comprising:
determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses;
determining the address being accessed by the instruction is within the range of MMIO addresses;
translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus, write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests,
wherein for each combination of bu

Assignees

• IBM

Inventors

• Raisch Christoph
• Kraemer Marco
• Otte Carsten
• Bradbury Jonathan D
• Craddock David

Classifications

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F2212/206

  Memory mapped I/O · CPC title