Bus-device-function address space mapping

Patent metadata

Field	Value
Publication number	US-10754808-B2
Application number	US-201515572436-A
Country	US
Kind code	B2
Filing date	Dec 20, 2015
Priority date	May 7, 2015
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.

First claim

The invention claimed is:

1. An apparatus comprising:
bridge logic to:
receive a request from a device, wherein the request references an address of a secondary address space, the secondary address space corresponds to a subset of addresses in a configuration address space of a system, the secondary address space corresponds to a first view of the configuration address space, and addresses in the second address space each comprise a respective Peripheral Component Interconnect (PCI)-based bus-device-function (BDF) number, wherein the secondary address space comprises a particular one of a plurality of non-overlapping secondary address spaces, each of the plurality of secondary address spaces maps to a respective portion of the configuration address space, and a particular BDF number is used in both the particular secondary address space and another one of the plurality of secondary address spaces; and
use a mapping table to translate the address of the particular secondary address space into a corresponding address in the configuration address space, wherein addresses of the configuration address space each comprise a respective PCI-based BDF number, and the mapping table maps BDF numbers in the secondary address space to BDF numbers in the configuration address space.

2. The apparatus of claim 1 , wherein the second view of the configuration address space comprises a view of a root complex of the configuration address space.

3. The apparatus of claim 2 , wherein the first view of the configuration address space comprises a view of the device of the configuration address space.

4. The apparatus of claim 1 , wherein the configuration address space comprises a Peripheral Component Interconnect (PCI)-based configuration address space.

5. The apparatus of claim 1 , wherein another subset of address in the configuration address space is mapped to addresses in a third another one of the plurality of secondary address spaces, and addressed in the other secondary address space each comprises a respective BDF number.

6. The apparatus of claim 1 , wherein each address in the particular secondary address space maps to exactly one respective address in the configuration address space.

7. The apparatus of claim 1 , wherein the configuration address space further comprises a subset of addresses reserved for hot-plugging.

8. The apparatus of claim 1 , wherein addresses in the configuration address space are enumerated to maximize utilization of available bus addresses within the configuration address space.

9. The apparatus of claim 8 , wherein addresses in the configuration address space are enumerated according to a first technique and addresses in the secondary address space are enumerated using a different second technique.

10. The apparatus of claim 9 , wherein the second technique is agnostic to maximizing available bus addresses within the secondary address space.

11. The apparatus of claim 1 , wherein the mapping table comprises two mapping tables, one for upstream translations, the second for downstream translations.

12. The apparatus of claim 1 , wherein the mapping table is stored in system memory, a pointer in local memory points to the mapping table, and the bridge logic access the mapping table using the pointer.

13. The apparatus of claim 1 , further comprising memory to store at least a portion of the mapping table locally for access by the bridge logic.

14. The apparatus of claim 1 , wherein the bridge logic is further to:
identify an update to the mapping table;
invalidate a local copy of at least a portion of the mapping table; and
replace the local copy with a new copy of at least a portion of the updated mapping table during runtime of the system.

15. At least one storage device within machine readable code stored thereon, the code executable by a processor to:
manage mapping tables for access by a mapping portal bridge to translate configuration address space addresses between a primary address domain and a plurality of secondary address domains defined for a system, wherein the primary address domain comprises a view of the configuration address space as viewed upstream from the mapping portal bridge and the secondary address domains comprise respective views of the configuration address space as viewed downstream from the mapping portal bridge, the primary address domain comprises a particular bus-device-function (BDF) number space, and each of the secondary address domains in the plurality of secondary address domains comprises a respective secondary BDF number space, wherein the mapping tables map each of the plurality of secondary address spaces to respective portions of the primary address domain, and a particular BDF number is used in more than one of the plurality of secondary address domains;
detect a change to the system; and
update the mapping tables based on the change.

16. A system comprising:
a root complex;
a mapping portal bridge coupled to a device and receiving data exchanged between the device and the root complex, wherein the mapping portal bridge comprises logic to:
receive a request from a device, wherein the request references an address of a secondary address space, wherein the secondary address space comprises one of a plurality of secondary address spaces and each of the plurality of secondary address spaces corresponds to a respective subset of addresses in a configuration address space of a system, each of the plurality of secondary address spaces corresponds to a first view of the configuration address space, addresses in the second address space each comprise a respective bus-device-function (BDF) number, and a same particular BDF number is reused in two or more of the plurality of second address spaces; and
use a mapping table to translate the address of a particular one of the plurality of secondary address spaces into a corresponding address in the configuration address space, wherein addresses of the configuration address space each comprise a respective BDF number, and the mapping table maps BDF numbers in the secondary address space to BDF numbers in the configuration address space.

17. The system of claim 16 , wherein the second view comprises a view of the root complex.

18. The system of claim 16 , further comprising system software to manage updates of the mapping table.

Assignees

• Intel Corp

Inventors

• Sethi Prashant
• Klinglesmith Michael T
• Harriman David J
• Rozic Reuven
• Kutuva Rabindrananth Shanthanand

Classifications

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title