Semiconductor dies having ultra-thin wafer backmetal systems, microelectronic devices containing the same, and associated fabrication methods

Patent metadata

Field	Value
Publication number	US-10923451-B2
Application number	US-201916513246-A
Country	US
Kind code	B2
Filing date	Jul 16, 2019
Priority date	Jul 16, 2019
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.

First claim

What is claimed is:

1. A method for processing a device wafer, comprising:
obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside;
sputter depositing a wafer-level gold-based ohmic bond layer onto the wafer backside, the wafer-level gold-based ohmic bond layer having a first average grain size and predominately composed of gold, by weight;
utilizing an electroplating process to deposit a wafer-level silicon (Si) ingress-resistant plated layer over the wafer-level gold-based ohmic bond layer, while imparting the wafer-level Si ingress-resistant plated layer with a second average grain size exceeding the first average grain size; and
singulating the device wafer to separate the device wafer into a plurality of semiconductor die each having a die frontside formed from a portion of the wafer frontside, a gold-based ohmic bond layer formed from a portion of the wafer-level gold-based ohmic bond layer, and an Si ingress-resistant plated layer formed from a portion of the wafer-level Si ingress-resistant plated layer.

2. The method of claim 1 further comprising sputter depositing the wafer-level gold-based ohmic bond layer to consist essentially of gold.

3. The method of claim 1 further comprising formulating the wafer-level Si ingress-resistant plated layer to be predominately composed of gold, by weight, while having a lower gold content than does the wafer-level gold-based ohmic bond layer.

4. The method of claim 1 further comprising formulating the wafer-level Si ingress-resistant plated layer to be predominately composed of gold, silver, palladium, platinum, or a combination thereof, by weight.

5. The method of claim 1 further comprising, when depositing the wafer-level Si ingress-resistant plated layer, controlling the electroplating process such that the second average grain size is at least ten times the first average grain size.

6. The method of claim 1 wherein controlling the electroplating process comprises maintaining a current density between about 0.5 and about 3.5 amp per square foot when depositing the wafer-level Si ingress-resistant plated layer.

7. The method of claim 1 further comprising:
sputter depositing the wafer-level gold-based ohmic bond layer directly onto the wafer backside; and
electroplating the wafer-level Si ingress-resistant plated layer directly onto the wafer-level gold-based ohmic bond layer.

8. The method of claim 1 further comprising sputter depositing the wafer-level gold-based ohmic bond layer to have an average thickness ranging from about 1 to about 10 kilo angstroms.

9. The method of claim 8 further comprising:
sputter depositing the wafer-level gold-based ohmic bond layer to have an average thickness ranging from about 3 to about 5 kilo angstroms; and
electroplating the wafer-level Si ingress-resistant plated layer to have an average thickness equal to or greater than the wafer-level gold-based ohmic bond layer.

10. The method of claim 1 further comprising, prior to the sputter depositing the wafer-level gold-based ohmic bond layer, removing material from the device wafer to impart the device wafer with a thickness less than 101.6 microns.

11. The method of claim 1 further comprising, for at least a first semiconductor die included in the plurality of semiconductor die, attaching the first semiconductor die to a substrate utilizing a sintered bond layer.

12. The method of claim 11 wherein attaching comprises:
applying a sinter precursor material at an interface between the first semiconductor die and the substrate; and
sintering the sinter precursor material at a maximum process temperature to transform the sinter precursor material into the sintered bond layer, the Si ingress-resistant plated layer inhibiting formation of silicon oxide at an interface between the sinter bond layer and the Si ingress-resistant plated layer during the sintering process.

13. A method for producing a microelectronic device, comprising:
obtaining a semiconductor die comprising a die backside, a gold-based ohmic bond layer formed on the die backside, and a silicon (Si) ingress-resistant plated layer formed on the gold-based ohmic bond layer, the Si ingress-resistant plated layer having an average grain size exceeding that of the gold-based ohmic bond layer;
placing the semiconductor die on a substrate having an upper surface;
before, after, or concurrent with placement of the semiconductor die on the substrate, applying a sinter precursor material at an interface between the semiconductor die and the upper surface of the substrate; and
sintering the sinter precursor material at a maximum process temperature to transform the sinter precursor material into a sintered bond layer contacting the Si ingress-resistant plated layer and bonding the semiconductor die to the substrate.

14. The method of claim 13 wherein the substrate comprises an electrically-conductive base flange, while the semiconductor die comprises a transistor; and
wherein the method further comprises electrically coupling a source region of the transistor to the electrically-conductive base flange through the gold-based ohmic bond layer, the Si ingress-resistant plated layer, and the sintered bond layer.

15. The method of claim 13 further comprising selecting the gold-based ohmic bond layer to consist essentially of gold.

16. The method of claim 13 further comprising selecting the Si ingress-resistant plated layer to be predominately composed of gold, by weight, while having a lower gold content than does the gold-based ohmic bond layer.

17. The method of claim 13 further comprising selecting the Si ingress-resistant plated layer to be predominately composed of gold, silver, palladium, platinum, or a combination thereof, by weight.

18. The method of claim 13 further comprising selecting the average grain size of the Si ingress-resistant plated layer to be at least ten times an average grain size of the gold-based ohmic bond layer.

19. The method of claim 13 further comprising selecting the gold-based ohmic bond layer to have an average thickness ranging from about 3 to about 5 kilo angstroms; and
further selecting the Si ingress-resistant plated layer to have an average thickness equal to or greater than the gold-based ohmic bond layer.

20. The method of claim 13 further comprising selecting the semiconductor die to have a thickness less than 101.6 microns.

Assignees

• Nxp Usa Inc

Inventors

• Sun Tianwei
• Molla Jaynal A

Classifications

• H10W72/551

  Materials of bond wires · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title