Memory device

Patent metadata

Field	Value
Publication number	US-10923189-B2
Application number	US-201916353172-A
Country	US
Kind code	B2
Filing date	Mar 14, 2019
Priority date	Sep 20, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

According to one embodiment, a memory device includes a memory cell including a resistance change memory element and a selector element, a word line, a bit line connected to one end of the memory cell, an operational amplifier including a non-inverting input connected to the bit line, an output circuit including a first terminal connected to an output of the operational amplifier, a second terminal connected to the bit line, and a charge/discharge circuit including a capacitor, a charge circuit and a discharge circuit, each including one end connected to an inverting input of the operational amplifier. At the time of falling of a write voltage for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell including a resistance change memory element in which a low resistance state or a high resistance state can be set according to a voltage decreasing speed of a write voltage signal to be applied across both terminals of the resistance change memory element, and a selector element connected in series to the resistance change memory element;
a word line to which a signal for selecting the memory cell is supplied;
a bit line connected to one end of the memory cell;
an operational amplifier including a non-inverting input terminal connected to the bit line, an inverting input terminal, and an output terminal;
an output circuit including a first terminal connected to the output terminal of the operational amplifier, a second terminal connected to the bit line, and a third terminal to which a predetermined potential is applied; and
a charge/discharge circuit which includes a capacitor, a charge circuit section charging the capacitor, and a discharge circuit section discharging the capacitor, and in which one end of the charge circuit section, one end of the discharge circuit section, and one end of the capacitor are connected to the inverting input terminal of the operational amplifier, wherein
at least at the time of decreasing of the write voltage signal for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit section and a potential of the other end of the capacitor.

2. The memory device of claim 1 , wherein
the selector element includes a three-terminal switch element, and
the word line is connected to a control terminal of the three-terminal switch element.

3. The memory device of claim 1 , wherein
the selector element includes a two-terminal switch element, and
the word line is connected to one of two terminals of the two-terminal switch element, the one of the two terminals being a terminal to which the resistance change memory element is not connected.

4. The memory device of claim 1 , wherein
the discharge circuit section includes a transistor, and a source of the transistor corresponds to the other end of the discharge circuit section.

5. The memory device of claim 1 , wherein
the output circuit includes a transistor, a gate of the transistor corresponds to the first terminal of the output circuit, a drain of the transistor corresponds to the second terminal of the output circuit, and a source of the transistor corresponds to the third terminal of the output circuit.

6. The memory device of claim 1 , wherein
an absolute value of a threshold voltage of a transistor in the output circuit is lower than an absolute value of a threshold voltage of a transistor in the charge circuit section or an absolute value of a threshold voltage of a transistor in the discharge circuit section within a range of 0.1 to 0.2V.

7. A memory device comprising:
a memory cell including a resistance change memory element in which a low resistance state or a high resistance state can be set according to a voltage decreasing speed of a write voltage signal to be applied across both terminals of the resistance change memory element, and a selector element connected in series to the resistance change memory element;
a word line to which a signal for selecting the memory cell is supplied;
a bit line connected to one end of the memory cell;
an operational amplifier including a non-inverting input terminal connected to the bit line, an inverting input terminal, and an output terminal;
an output circuit including a first terminal connected to the output terminal of the operational amplifier, a second terminal connected to the bit line, and a third terminal to which a predetermined potential is applied; and
a charge/discharge circuit which includes a capacitor, a charge circuit section charging the capacitor, and a discharge circuit section discharging the capacitor, and in which one end of the charge circuit section, one end of the discharge circuit section, and one end of the capacitor are connected to the inverting input terminal of the operational amplifier, wherein
the operational amplifier includes a first transistor of a first conductivity type, a second transistor of the first conductivity type, and a third transistor of the first conductivity type,
a source of the first transistor, a source of the second transistor, and a drain of the third transistor are connected to each other,
a gate of the first transistor corresponds to the inverting input terminal of the operational amplifier, a gate of the second transistor corresponds to the non-inverting input terminal of the operational amplifier, and a drain of the first transistor corresponds to the output terminal of the operational amplifier, and
to a gate of the third transistor, a signal according to a variation of a signal to be input to the gate of the first transistor is input.

8. The memory device of claim 7 , wherein
the operational amplifier further includes a fourth transistor of a second conductivity type and a fifth transistor of the second conductivity type,
a drain of the fourth transistor is connected to the drain of the first transistor, and
a drain of the fifth transistor is connected to a drain of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor.

9. The memory device of claim 7 , wherein
to the gate of the third transistor, a signal common to a signal to be input to the gate of the first transistor is input.

10. The memory device of claim 8 , wherein
the operational amplifier further includes a sixth transistor of the first conductivity type and a seventh transistor of the first conductivity type,
the drain of the fourth transistor is connected to a drain of the sixth transistor,
the drain of the fifth transistor is connected to a drain of the seventh transistor, and
to a gate of the sixth transistor and a gate of the seventh transistor, a certain potential is applied.

11. The memory device of claim 10 , wherein
an absolute value of a threshold voltage of each of the first, second, sixth, and seventh transistors is higher than an absolute value of a threshold voltage of a transistor in the charge circuit section and an absolute value of a threshold voltage of a transistor in the discharge circuit section within a range of 0.1 to 0.2V.

Assignees

• Toshiba Memory Corp

Inventors

• Ogiwara Ryu
• Takashima Daisaburo
• Iizuka Takahiko

Classifications

• H03F2203/45674

  the LC comprising one current mirror · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• H03F2203/45728

  the LC comprising one switch · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title