Devices and methods to program a memory cell

Patent metadata

Field	Value
Publication number	US-9496035-B2
Application number	US-201514804122-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Mar 11, 2011
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

First claim

What is claimed is:

1. A memory device, comprising:
a controller configured to operate in a voltage mode and a current mode to transition a memory cell between high and low resistance states, the controller comprising:
a selector configured to select operation of the controller in the voltage mode or the current mode;
a voltage ramp node configured to produce a decreasing voltage programming signal for application to the memory cell in the voltage mode; and
a current ramp node configured to produce a decreasing current programming signal for application to the memory cell in the current mode, wherein the controller is configured to apply the decreasing voltage programming signal or the decreasing current programming signal to the memory cell after the memory cell enters the melting phase to transition the memory cell between the high and low resistance states.

2. The memory device of claim 1 , further comprising:
a voltage reference configured to generate a voltage signal to provide a voltage programming signal to the memory cell in the voltage mode; and
a current reference configured to generate a current signal to provide a current programming signal to the memory cell in the current mode, wherein the controller is configured to apply the voltage programming signal or the current programming signal to the memory cell until the memory cell enters a melting phase.

3. The memory device of claim 2 , wherein the controller is further configured to apply the current programming signal to the memory cell to transition the memory cell from the low resistance state to the high resistance state.

4. The memory device of claim 3 , wherein the controller is further configured to apply the decreasing current programming signal after the memory cell enters the melting phase.

5. The memory device of claim 2 , wherein the controller is further configured to apply the voltage programming signal to the memory cell to transition the memory cell from the high resistance state to the low resistance state.

6. The memory device of claim 5 , wherein the controller is further configured to apply the decreasing voltage programming signal to the memory cell after the memory cell enters the melting phase to transition the memory cell from the high resistance state to the low resistance state.

7. The memory device of claim 1 , further comprising:
a plurality of gates to mirror the decreasing voltage programming signal produced by the voltage ramp node to provide a mirrored voltage programming signal or to mirror the decreasing current programming signal produced by the current ramp node to provide a mirrored current programming signal,
wherein the controller is configured to apply the mirrored voltage programming signal or the mirrored current programming signal to a bitline of the memory cell.

8. The memory device of claim 1 , wherein the voltage ramp node is configured to produce a substantially linearly decreasing voltage programming signal and the current ramp node is configured to produce a substantially linearly decreasing current programming signal.

9. The memory device of claim 1 , wherein the memory cell comprises one high resistance state and one low resistance state.

10. The memory device of claim 1 , wherein the selector comprises a plurality of transmission gates and at least one of the plurality of transmission gates being configured to turn on to select operation in the voltage mode or the current mode.

11. A system, comprising:
a memory array comprising a memory cell; and
a controller configured to operate in a voltage mode and in a current mode to transition the memory cell between high and low resistance states, the controller comprising:
a selector configured to select operation of the controller in the voltage mode or the current mode;
a voltage ramp node configured to produce a decreasing voltage programming signal for application to the memory cell in the voltage mode; and
a current ramp node configured to produce a decreasing current programming signal for application to the memory cell in the current mode, wherein the controller is configured to apply the decreasing voltage programming signal or the decreasing current programming signal to the memory cell after the memory cell enters the melting phase to transition the memory cell between the high and low resistance states.

12. The system of claim 11 , further comprising:
a voltage reference configured to generate a voltage signal to provide a voltage programming signal to the memory cell in the voltage mode; and
a current reference configured to generate a current signal to provide a current programming signal to the memory cell in the current mode, wherein the controller is configured to apply the voltage programming signal or the current programming signal to the memory cell until the memory cell enters a melting phase.

13. The system of claim 12 , wherein the controller is configured to apply the current programming signal to the memory cell to transition the memory cell from the low resistance state to the high resistance state, and to apply the decreasing current programming signal to the memory cell after the memory cell enters the melting phase.

14. The system of claim 12 , wherein the controller is further configured to apply the voltage programming signal to the memory cell to transition the memory cell from the high resistance state to the low resistance state, and apply the decreasing voltage programming signal to the memory cell after the memory cell enters the melting phase.

15. The system of claim 12 , wherein the controller is further configured to maintain the voltage programming signal at a voltage value or the current programming signal at a current value until the memory cell enters the melting phase.

16. The system of claim 11 , wherein the controller is further configured to compare the decreasing current programming signal produced by the current ramp node and a threshold current value, wherein the controller is configured to cease application of the decreasing current programming signal if the decreasing current programming signal is lower than the threshold current value.

17. The system of claim 11 , wherein the controller is further configured to compare the decreasing voltage programing signal produced by the voltage ramp node and a threshold voltage value, wherein the controller is configured to cease application of the decreasing voltage programming signal if the decreasing voltage programing signal is lower than the threshold voltage value.

18. The system of claim 17 , wherein the controller further comprises a differential amplifier for comparing the decreasing voltage programing signal and the threshold voltage value.

19. The system of claim 11 , wherein the controller further comprises a cascode configuration for operating in the voltage mode.

20. The system of claim 11 , wherein the memory cell comprises phase change memory (PCM).

Assignees

• Micron Technology Inc
• Ovonyx Memory Tech Llc

Inventors

• Di Vincenzo Umberto
• Lisi Carlo

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title

• G11C2013/009

  Write using potential difference applied between cell electrodes · CPC title