Error correction code circuits, semiconductor memory devices and memory systems

Patent metadata

Field	Value
Publication number	US-10922171-B2
Application number	US-201916441287-A
Country	US
Kind code	B2
Filing date	Jun 14, 2019
Priority date	Dec 17, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

First claim

What is claimed is:

1. An error correction code (ECC) circuit of a semiconductor memory device, the ECC circuit comprising:
a syndrome generation circuit configured to generate a syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal, the message including system check bits;
an ECC encoder configured to generate the first parity bits based on the message; and
a correction circuit configured to
receive the codeword,
correct at least a portion of (t1+t2) error bits in the codeword, based on the syndrome, wherein t1 and t2 are natural numbers, and
output a corrected message.

2. The ECC circuit of claim 1 , wherein the syndrome generation circuit includes
a switch circuit configured to
receive the first parity check matrix and the second parity check matrix, and
select one of the first parity check matrix and the second parity check matrix in response to the decoding mode signal, and

a syndrome generator, connected to the switch circuit, configured to generate the syndrome based on the codeword by using the selected parity check matrix.

3. The ECC circuit of claim 2 , wherein
the switch circuit is further configured to select the first parity check matrix if the decoding mode signal designates a first decoding mode, and
the syndrome generator is further configured to generate the syndrome based on the codeword by using the first parity check matrix, if the decoding mode signal designates the first decoding mode.

4. The ECC circuit of claim 3 , wherein
the correction circuit is further configured to correct (t1+t2) error bits in the codeword based on the syndrome.

5. The ECC circuit of claim 2 , wherein
the switch circuit is further configured to select the second parity check matrix if the decoding mode signal designates a second decoding mode; and
the syndrome generator is further configured to generate the syndrome based on the codeword by using the second parity check matrix, if the decoding mode signal designates the second decoding mode.

6. The ECC circuit of claim 5 , wherein
the correction circuit is configured to correct t2 error bits in the codeword based on the syndrome.

7. The ECC circuit of claim 1 , wherein the correction circuit includes:
an error locator polynomial calculator configured to calculate coefficients of an error locator polynomial based on the syndrome;
an error location calculator configured to generate an error location signal indicating a location of at least one error bit in the codeword, based on the error locator polynomial having the calculated coefficients; and
a data corrector configured to
correct the at least one error bit in the codeword based on the error location signal, and
output the corrected message.

8. The ECC circuit of claim 1 , further comprising:
a mode selector configured to generate the decoding mode signal.

9. The ECC circuit of claim 1 , further comprising:
a memory configured to store the first parity check matrix and the second parity check matrix, wherein
the first parity check matrix includes the second parity check matrix and a system parity check matrix, and
a memory controller is configured to
generate the system parity check matrix,
transmit the message to the semiconductor memory device, and
use the system parity check matrix in ECC decoding.

10. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
an error correction code (ECC) circuit configured to
generate a codeword by performing ECC encoding on a message received from a memory controller, the message including system parity bits encoded by the memory controller based on a first generation matrix, and the codeword being generated based on a second generation matrix,
generate a syndrome based on the message and first parity bits in a read codeword from the memory cell array,
correct at least a portion of (t1+t2) error bits in the read codeword based on the syndrome, wherein t1 and t2 are natural numbers, and
output a corrected message; and
a control logic circuit configured to control the ECC circuit based on a command and an address received from the memory controller.

11. The semiconductor memory device of claim 10 , wherein
the error correction code circuit is configured to correct fewer than or equal to t2 error bits, and
the memory controller is configured to
transmit the message to the semiconductor memory device, and
correct fewer than or equal to t1 error bits.

12. The semiconductor memory device of claim 10 , wherein the ECC circuit includes:
an ECC encoder configured to perform the ECC encoding on the message; and
an ECC decoder, including:
a syndrome generation circuit configured to generate the syndrome based on the message and the first parity bits by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal; and
a correction circuit configured to correct at least the portion of (t1+t2) error bits in the codeword based on the syndrome and configured to output the corrected message.

13. The semiconductor memory device of claim 12 , wherein the syndrome generation circuit includes:
a switch circuit configured to
receive the first parity check matrix and the second parity check matrix, and
select one of the first parity check matrix and the second parity check matrix in response to the decoding mode signal, and

a syndrome generator, connected to the switch circuit, configured to generate the syndrome based on the codeword by using the selected parity check matrix.

14. The semiconductor memory device of claim 13 , wherein
the switch circuit is further configured to select the first parity check matrix if the decoding mode signal designates a first decoding mode,
the syndrome generator is further configured to generate the syndrome based on the codeword by using the first parity check matrix if the decoding mode signal designates the first decoding mode, and
the correction circuit is further configured to correct (t1+t2) error bits in the codeword based on the syndrome.

15. The semiconductor memory device of claim 13 , wherein
the switch circuit is further configured to select the second parity check matrix if the decoding mode signal designates a second decoding mode,
the syndrome generator is further configured to generate the syndrome based on the codeword by using the second parity check matrix, if the decoding mode signal designates the second decoding mode, and
the correction circuit is further configured to correct t2 error bits in the codeword based on the syndrome.

16. The semiconductor memory device of claim 12 , wherein the ECC circuit further includes:
a mode selector configured to generate the decoding mode signal based on a control signal; and
a memory configured to store the second generation matrix, the first parity check matrix and the second parity check matrix, wherein
the first parity check matrix includes the second parity check matrix and a system parity check matrix, and
the memory controller is configured to use the system parity check matrix in ECC decoding.

17. The semiconductor memory device of claim 12 , wherein
each of the plurality of memory cells includes a dynamic memory cell,
the first parity check matrix represents a double error correction (DEC) code, and
the second parity check matrix represe

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Sung-Hye
• Lee Ki-Jun
• Lee Myung-Kyu
• Kong Jun Jin

Classifications

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/11 Primary

  using multiple parity bits · CPC title

• G11C29/781

  combined in a redundant decoder · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title