Method for memory scrub of DRAM with internal error correcting code (ECC) bits during either memory activate and/or precharge operation

Patent metadata

Field	Value
Publication number	US-9823964-B2
Application number	US-201514963067-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Dec 8, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A method for updating a DRAM memory array is disclosed. The method comprises: a) receiving a command from a memory controller to initiate an active cycle for activating a memory row in a DRAM memory array; b) performing an Error Correction Code (ECC) scrub on the memory row prior to reading data from the memory row into sense amplifiers in the DRAM memory array in accordance with the command to activate; c) activating the memory row; and d) writing corrected data following the ECC scrub back into memory from the sense amplifiers during a pre-charge cycle of the DRAM memory array.

First claim

What is claimed is:

1. A method for updating a DRAM memory array, said method comprising:
a) receiving a command from a memory controller to initiate an active cycle for activating a memory row in a DRAM memory array;
b) performing an Error Correction Code (ECC) scrub on the memory row in the DRAM memory array in accordance with the command to activate;
c) activating the memory row; and
d) writing corrected data following the ECC scrub back into the memory row of the DRAM memory array from the sense amplifiers during a pre-charge cycle of the DRAM memory array.

2. The method of claim 1 , further comprising:
e) incrementing a column counter internal to the DRAM memory array to track columns scrubbed of the DRAM memory array.

3. The method of claim 2 , further comprising:
repeating the a), b), c), d) and e) for a subsequent row in the DRAM memory array.

4. The method of claim 3 , wherein the command to activate comprises a tagged extension to indicate that an ECC scrub is to be performed during the activate cycle.

5. The method of claim 3 , wherein the DRAM is configured to perform the ECC scrub of a memory row during every activate cycle.

6. The method of claim 1 , wherein the DRAM memory array is configured with a plurality of error correction modules operable to scrub a plurality of columns of the memory row at the same time.

7. The method of claim 6 , wherein the ECC scrub comprises:
reading in data from the memory row;
checking ECC bits corresponding to the plurality of columns in the memory row;
correcting the data for the plurality of columns if the ECC bits indicate an error;
re-computing the ECC bits for the plurality of columns; and
writing corrected data and the ECC bits back into the DRAM memory array.

8. A method for updating a DRAM memory array, said method comprising:
a) activating a memory row in a DRAM memory array during an activate cycle;
b) receiving a command from the memory controller to initiate a precharge cycle for precharging the memory row in the DRAM memory array;
c) performing an Error Correction Code (ECC) scrub on the memory row prior to writing corrected data from the sense amplifiers back into the DRAM memory array in accordance with the precharge command; and
d) writing corrected data following the ECC scrub back into the memory row of the DRAM memory array from the sense amplifiers during a pre-charge cycle of the DRAM memory array.

9. The method of claim 8 , further comprising:
e) incrementing a column counter internal to the DRAM memory array to track columns that have been scrubbed in the DRAM memory array.

10. The method of claim 9 , further comprising:
repeating the a), b), c), d), and e) for a subsequent row in the DRAM memory array.

11. The method of claim 10 , wherein the command to precharge comprises a tagged extension to indicate that an ECC scrub should be performed during the precharge cycle.

12. The method of claim 10 , wherein the DRAM is configured to perform the ECC scrub during every precharge cycle.

13. The method of claim 10 , wherein the DRAM memory array is configured with a plurality of error correction modules operable to scrub a plurality of columns of the memory row at the same time.

14. The method of claim 10 , wherein the ECC scrub comprises:
reading in data from the memory row;
checking ECC bits corresponding to the plurality of columns in the memory row;
correcting the data for the plurality of columns if the ECC bits indicate an error;
re-computing the ECC bits for the plurality of columns; and
writing corrected data and the ECC bits back into the DRAM memory array.

15. An apparatus for updating a DRAM memory array, said apparatus comprising:
a memory controller; and
the DRAM memory array, wherein the DRAM memory array is configured to:
a) receive a command from a memory controller to initiate an active cycle for activating a memory row in a DRAM memory array;
b) perform an Error Correction Code (ECC) scrub on the memory row in the DRAM memory array in accordance with the command to activate;
c) activate the memory row; and
d) write corrected data following the ECC scrub back into the memory row of the DRAM memory array from the sense amplifiers during a pre-charge cycle of the DRAM memory array.

16. The apparatus of claim 15 , wherein the DRAM memory array is further configured to:
repeat the a), b), c), and d) for a subsequent row in the DRAM memory array.

17. The apparatus of claim 15 , wherein the command to activate comprises a tagged extension to indicate that an ECC scrub is to be performed during the activate cycle.

18. The apparatus of claim 15 , wherein the DRAM memory array is configured to perform the ECC scrub of a memory row during every activate cycle.

19. The apparatus of claim 15 , wherein the DRAM memory array is configured with a plurality of error correction modules operable to scrub a plurality of columns of the memory row at the same time.

20. The apparatus of claim 15 , wherein in order to perform the ECC scrub the DRAM memory array is configured to:
read in data from the memory row;
check ECC bits corresponding to the plurality of columns in the memory row;
correct the data for the plurality of columns if the ECC bits indicate an error;
re-compute the ECC bits for the plurality of columns; and
write corrected data and the ECC bits back into the DRAM memory array.

Assignees

• Nvidia Corp

Inventors

• Reed David
• Gupta Alok

Classifications

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C2211/4062

  Parity or ECC in refresh operations · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C2029/0409

  Online test · CPC title