Methods for forming single crystal silicon ingots with improved resistivity control

Patent metadata

Field	Value
Publication number	US-10920337-B2
Application number	US-201715855466-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Dec 28, 2016
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

Methods for forming single crystal silicon ingots with improved resistivity control and, in particular, methods that involve gallium or indium doping are disclosed. In some embodiments, the ingots are characterized by a relatively high resistivity.

First claim

What is claimed is:

1. A method for producing a single crystal silicon product ingot, the method comprising:
adding polycrystalline silicon to a crucible;
heating the polycrystalline silicon to cause a silicon melt to form in the crucible;
adding a first dopant selected from the group consisting of gallium and indium to the crucible to form a silicon melt comprising silicon and the first dopant;
pulling a sample ingot from the silicon melt comprising silicon and the first dopant, the sample ingot having a resistivity, there being a silicon melt comprising silicon and first dopant disposed in the crucible after the sample ingot is pulled;
measuring the resistivity of the sample ingot;
adding an amount of phosphorous as a second dopant to the silicon melt comprising silicon and the first dopant to form a silicon melt comprising silicon, the first dopant and phosphorous, phosphorous being added after the resistivity of the sample ingot is measured, the amount of phosphorous added to the silicon melt being based at least in part on the measured resistivity of the sample ingot; and
pulling the single crystal silicon product ingot from the silicon melt comprising silicon, the first dopant and phosphorous.

2. The method as set forth in claim 1 wherein the amount of phosphorous added to the silicon melt comprising silicon and the first dopant is based at least in part on a target resistivity of at least a portion of the single crystal silicon product ingot.

3. The method as set forth in claim 2 wherein the target resistivity is a minimum resistivity.

4. The method as set forth in claim 3 wherein the minimum resistivity is at least about 1,500 Ω-cm.

5. The method as set forth in claim 2 wherein the target resistivity is a maximum resistivity.

6. The method as set forth in claim 1 wherein the first dopant is gallium.

7. The method as set forth in claim 6 wherein the melt comprising gallium has a concentration of gallium in the melt after gallium is added to the crucible, the concentration of gallium being less than about 0.5 ppma.

8. The method as set forth in claim 6 wherein gallium is added to the crucible as a silicon-gallium alloy.

9. The method as set forth in claim 1 wherein the first dopant is indium.

10. The method as set forth in claim 9 wherein the melt comprising indium has a concentration of indium in the melt after indium is added to the crucible, the concentration of indium being less than about 0.5 ppma.

11. The method as set forth in claim 9 wherein indium is added to the crucible as a silicon-indium alloy.

12. The method as set forth in claim 1 wherein the measured resistivity of the sample ingot is about 10,000 ohm-cm or less.

13. The method as set forth in claim 1 wherein the polycrystalline silicon is semiconductor grade silicon.

14. The method as set forth in claim 1 comprising measuring the resistivity of the sample ingot with a four-point resistivity probe.

Assignees

• Sunedison Semiconductor Ltd
• Globalwafers Co Ltd

Inventors

• Phillips Richard J
• Daggolu Parthiv
• Gitlin Eric
• Standley Robert
• Lee Hyungmin
• Zhang Nan
• Ryu Jae-Woo
• Basak Soubir

Classifications

• C30B15/04 Primary

  adding doping materials, e.g. for n-p-junction · CPC title

• C30B29/06

  Silicon · CPC title

• C30B15/20 Primary

  Controlling or regulating (controlling or regulating in general G05) · CPC title