Method of fabricating a flash memory

Patent metadata

Field	Value
Publication number	US-10916634-B2
Application number	US-201916417542-A
Country	US
Kind code	B2
Filing date	May 20, 2019
Priority date	May 20, 2019
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
providing a substrate;
forming a memory gate on said substrate and a hard mask layer on said memory gate;
forming an oxide spacer on a sidewall of said memory gate and said hard mask layer;
forming a select gate on a sidewall of said oxide spacer, wherein said oxide spacer is between said select gate and said sidewall of said memory gate and said hard mask layer;
performing a selective oxidation process to form an oxide layer on said hard mask layer and said select gate, wherein a portion of said oxide layer on said select gate is thicker than a portion of said oxide layer on said hard mask layer; and
performing an etch process to completely remove said portion of said oxide layer on said hard mask layer and said hard mask layer to expose a top surface of said memory gate.

2. The method of fabricating a semiconductor device of claim 1 , wherein said portion of said oxide layer on said select gate is thinned by said etch process and remains on said select gate.

3. The method of fabricating a semiconductor device of claim 1 , wherein said etch process comprises a dry etch process, a wet clean process or the combination thereof.

4. The method of fabricating a semiconductor device of claim 1 , wherein said oxide layer is not formed on said oxide spacer.

5. The method of fabricating a semiconductor device of claim 1 , wherein said oxide layer and said oxide spacer completely surround said select gate.

6. The method of fabricating a semiconductor device of claim 1 , wherein said selective oxidation process is rapid thermal process.

7. The method of fabricating a semiconductor device of claim 1 , further comprising forming an etch stop layer between said hard mask layer and said memory gate.

8. The method of fabricating a semiconductor device of claim 1 , further comprising forming an oxide-nitride-oxide trilayer between said substrate and said memory gate.

9. The method of fabricating a semiconductor device of claim 1 , a material of said select gate comprises polysilicon.

10. The method of fabricating a semiconductor device of claim 1 , a material of said hard mask layer comprises silicon nitride.

Assignees

• United Microelectronics Corp

Inventors

• Xu Wei
• Ding Wenbo
• Chen Yu-Yang
• Xiang Wang

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title