Three-dimensional memory device including electrically conductive layers with molybdenum-containing liners

Patent metadata

Field	Value
Publication number	US-10916504-B2
Application number	US-201916441439-A
Country	US
Kind code	B2
Filing date	Jun 14, 2019
Priority date	Jun 14, 2019
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein each of the electrically conductive layers comprises a molybdenum-containing conductive liner and a metal fill portion comprising a metal other than molybdenum; and
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
wherein the molybdenum-containing conductive liner is located directly on a blocking dielectric layer; and
wherein the molybdenum-containing conductive liner has a thickness of 0.5 nm to 5 nm.

2. The three-dimensional memory device of claim 1 , wherein the molybdenum-containing conductive liner consists essentially of molybdenum.

3. The three-dimensional memory device of claim 1 , wherein the molybdenum-containing conductive liner comprises a material selected from molybdenum nitride or molybdenum carbide.

4. The three-dimensional memory device of claim 1 , wherein the molybdenum-containing conductive liner comprises a layer stack including a molybdenum layer consisting essentially of molybdenum and a molybdenum compound layer including a molybdenum compound selected from molybdenum nitride or molybdenum carbide.

5. The three-dimensional memory device of claim 1 , wherein the metal fill portion consists essentially of the metal other than molybdenum.

6. The three-dimensional memory device of claim 5 , wherein the metal fill portion consists essentially of an elemental metal selected from tungsten, cobalt, ruthenium, or copper.

7. The three-dimensional memory device of claim 1 , wherein the blocking dielectric layer is located between each of the electrically conductive layers and each of the memory stack structures.

8. The three-dimensional memory device of claim 7 , wherein the blocking dielectric layer comprises aluminum oxide, and wherein the metal fill portion consists essentially of tungsten.

9. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a three-dimensional NAND memory device;
the electrically conductive layers comprise word lines of the three-dimensional NAND memory device;
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

10. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structures;
forming a backside blocking dielectric layer in the backside recesses; and
forming electrically conductive layers in the backside recesses, wherein each of the electrically conductive layers comprise a molybdenum-containing conductive liner formed directly on the backside blocking dielectric layer, and a metal fill portion comprising a metal other than molybdenum.

11. The method of claim 10 , wherein the molybdenum-containing conductive liner consists essentially of molybdenum.

12. The method of claim 10 , wherein:
the molybdenum-containing conductive liner comprises molybdenum nitride; and
the molybdenum-containing conductive liner is formed by deposition of a molybdenum layer and nitridation of the molybdenum layer.

13. The method of claim 10 , wherein:
the molybdenum-containing conductive liner comprises molybdenum carbide; and
the molybdenum-containing conductive liner is formed by simultaneously or alternately providing a molybdenum precursor gas and a carbon precursor gas into the backside recesses and inducing thermal decomposition thereof.

14. The method of claim 10 , wherein the molybdenum-containing conductive liner comprises a layer stack including a molybdenum layer consisting essentially of molybdenum and a molybdenum compound layer including a molybdenum compound selected from molybdenum nitride or carbon-doped molybdenum.

15. The method of claim 10 , wherein the molybdenum-containing conductive liner has a thickness of 0.5 nm to 5 nm.

16. The method of claim 10 , wherein forming the molybdenum-containing conductive liner comprises inducing thermal decomposition of MoO 2 Cl 2 within the backside recesses.

17. The method of claim 10 , wherein the metal fill portion consists essentially of tungsten.

18. The method of claim 10 , further comprising:
forming a terrace region in the alternating stack, wherein the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack;
forming a retro-stepped dielectric material portion over the stepped surfaces; and

forming support pillar structures through the retro-stepped dielectric material portion and through the stepped surfaces.

19. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein each of the electrically conductive layers comprises a molybdenum-containing conductive liner and a metal fill portion comprising a metal other than molybdenum; and
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
wherein:
the molybdenum-containing conductive liner is located directly on a blocking dielectric layer;
the three-dimensional memory device comprises a three-dimensional NAND memory device;
the electrically conductive layers comprise word lines of the three-dimensional NAND memory device;
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

Assignees

• Sandisk Technologies Llc

Inventors

• Mukae Yusuke
• Takeguchi Naoki
• Yamaguchi Kensuke
• Makala Raghuveer S
• Terasawa Yujin

Classifications

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H01L27/11582

  Electricity · mapped topic