Dual silicide liner flow for enabling low contact resistance

Patent metadata

Field	Value
Publication number	US-10916471-B2
Application number	US-201916669643-A
Country	US
Kind code	B2
Filing date	Oct 31, 2019
Priority date	Oct 30, 2015
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor device, comprising:
depositing a sacrificial liner in self-aligned contact openings in first and second regions, where the first region includes a first device type and the second region includes a second device type;
filling the self-aligned contact openings with a sacrificial material;
completely removing the sacrificial material from the first region exposing the sacrificial liner;
removing a first mask from the second region and completely removing the sacrificial liner from the first region;
forming a first liner in the self-aligned contact openings of the first region;
forming first contacts in the first region on the first liner; and
completely removing the sacrificial material and the sacrificial liner from the second region after the first contacts are formed.

2. The method as recited in claim 1 , further comprising removing a second mask from the first region exposing the first contacts.

3. The method as recited in claim 2 , further comprising forming a second liner in the self-aligned contact openings of the second region.

4. The method as recited in claim 3 , further comprising forming second contacts in the second region.

5. The method as recited in claim 4 , wherein filling the self-aligned contact openings with the sacrificial material includes filling the self-aligned contact openings with TiN.

6. The method as recited in claim 5 , wherein depositing the sacrificial liner includes depositing an oxide liner.

7. The method as recited in claim 6 , wherein the first region includes an n-type field effect transistor (NFET) region and forming the first liner includes forming the first liner from one of Ti or TiN.

8. The method as recited in claim 7 , wherein the second region includes a p-type field effect transistor (PFET) region and forming the second liner includes forming the second liner from one of Pt, Ni or a combination thereof.

9. The method as recited in claim 8 , wherein the first contacts and the second contacts include different materials.

10. The method as recited in claim 9 , wherein the self-aligned contact openings include only one liner in the first region and only one liner in the second region and the first liner and the second liner include different materials.

11. The method as recited in claim 10 , wherein the first liner and the second liner form silicides.

12. A method for fabricating a semiconductor device, comprising:
patterning an interlevel dielectric layer to form self-aligned contact openings over field effect transistors;
depositing a sacrificial liner in the self-aligned contact openings;
filling the self-aligned contact openings with a sacrificial material;
completely removing the sacrificial material from an n-type field effect transistor (NFET) region exposing the sacrificial liner;
removing a first mask from a p-type field effect transistor (PFET) region and completely removing the sacrificial liner from the NFET region;
forming a first liner in the self-aligned contact openings of the NFET region;
forming first contacts in the NFET region on the first liner; and
completely removing the sacrificial material and the sacrificial liner from the PFET region after the first contacts are formed.

13. The method as recited in claim 12 , further comprising removing a second mask from the NFET region exposing the first contacts.

14. The method as recited in claim 13 , further comprising forming a second liner in the self-aligned contact openings of the PFET region.

15. The method as recited in claim 14 , further comprising forming second contacts in the PFET region.

16. The method as recited in claim 15 , wherein filling the self-aligned contact openings with the sacrificial material includes filling the self-aligned contact openings with TiN.

17. The method as recited in claim 16 , wherein depositing the sacrificial liner includes depositing an oxide liner.

18. The method as recited in claim 17 , wherein forming the first liner includes forming the first liner from one of Ti or TiN.

19. The method as recited in claim 18 , wherein forming the second liner includes forming the second liner from one of Pt, Ni or a combination thereof.

20. The method as recited in claim 19 , wherein the self-aligned contact openings include only one liner in the NFET region and only one liner in the PFET region and the first liner and the second liner include different materials.

Assignees

• IBM
• Elpis Tech Inc

Inventors

• Adusumilli Praneet
• Basker Veeraraghavan S
• Liu Zuoguang
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title