System of improved loop detection and execution

Patent metadata

Field	Value
Publication number	US-9459871-B2
Application number	US-201213731377-A
Country	US
Kind code	B2
Filing date	Dec 31, 2012
Priority date	Dec 31, 2012
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

A method, system, and computer program product for identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination is made of whether the last iteration of the loop is done. If the last iteration is not done, then embodiments continue replaying the loop instructions, until the last iteration is done.

First claim

What is claimed is:

1. A method comprising:
detecting, by a controller, a loop hint instruction characterizing a loop including a plurality of loop instructions, before any execution of the loop instructions occurs, wherein the loop hint instruction includes a loop iteration information specifying whether the loop is an indefinite loop or a definite loop, wherein a definite loop count is specified for the definite loop and no definite loop count is specified for the indefinite loop;
storing loop information including the loop hint instruction and the loop instructions into an instruction queue;
executing the loop instructions in a first iteration;
counting a loop iteration based on the loop information;
determining whether a last iteration of the loop instructions is completed; and
replaying the loop instructions from the instruction queue for execution until the last iteration is completed,
wherein at least one of delay time and power consumption is reduced.

2. The method of claim 1 , wherein the controller marks the loop instructions in the queue, based on the loop information.

3. The method of claim 1 , wherein the loop hint instruction and the plurality of loop instructions are contained in fetch parcels obtained from a cache, and wherein the loop hint instruction further includes (i) a start instruction offset inside the loop's first fetch parcel, (ii) an end instruction offset inside the loop's last fetch parcel, and (iii) a total number of fetch parcels in the loop including the first and last fetch parcels.

4. A method comprising:
identifying, by a controller, loop information corresponding to a plurality of loop instructions, before any execution of the loop instructions occurs;
storing the loop instructions into a queue;
executing the loop instructions in a first iteration;
counting a loop iteration based on the identified loop information;
determining whether a last iteration of the loop instructions is completed; and
replaying the loop instructions from the queue for execution until the last iteration is completed,
wherein at least one of delay time and power consumption is reduced, and wherein the controller updates the loop instructions in the queue, based on historical execution information, by replacing an indefinite loop with a definite loop by a local change via self-modifying code.

5. The method of claim 1 , wherein the queue predictively executes an outside-loop instruction after the last iteration is completed without a mispredict that would require an instruction pipeline flush.

6. The method of claim 1 , wherein the controller detects illegal conditions of the loop and aborts the loop before the loop instructions are replayed.

7. A non-transitory computer readable medium, storing instructions executable by a processor to perform:
detecting, by a controller, a loop hint instruction characterizing a loop including a plurality of loop instructions, before any execution of the loop instructions occurs, wherein the loop hint instruction includes a loop iteration information specifying whether the loop is an indefinite loop or a definite loop, wherein a definite loop count is specified for the definite loop and no definite loop count is specified for the indefinite loop;
storing loop information including the loop hint instruction and the loop instructions into an instruction queue;
executing the loop instructions in a first iteration;
counting a loop iteration based on the loop information;
determining whether a last iteration of the loop instructions is completed; and
replaying the loop instructions from the instruction queue for execution until the last iteration is completed,
wherein at least one of delay time and power consumption is reduced.

8. The non-transitory computer readable medium of claim 7 , wherein the controller marks the loop instructions in the queue, based on the loop information.

9. The non-transitory computer readable medium of claim 7 , wherein the loop hint instruction and the plurality of loop instructions are contained in fetch parcels obtained from a cache, and wherein the loop hint instruction further includes (i) a start instruction offset inside the loop's first fetch parcel, (ii) an end instruction offset inside the loop's last fetch parcel, and (iii) a total number of fetch parcels in the loop including the first and last fetch parcels.

10. A non-transitory computer readable medium, storing instructions executable by a processor to perform:
identifying, by a controller, loop information corresponding to a plurality of loop instructions, before any execution of the loop instructions occurs;
storing the loop instructions into a queue;
executing the loop instructions in a first iteration;
counting a loop iteration based on the identified loop information;
determining whether a last iteration of the loop instructions is completed; and
replaying the loop instructions from the queue for execution until the last iteration is completed,
wherein at least one of delay time and power consumption is reduced, and wherein the controller updates the loop instructions in the queue, based on historical execution information, by replacing an indefinite loop with a definite loop by a local change via self-modifying code.

11. The non-transitory computer readable medium of claim 7 , wherein the queue predictively executes an outside-loop instruction after the last iteration is completed without a mispredict that would require an instruction pipeline flush.

12. The non-transitory computer readable medium of claim 7 , wherein the controller detects illegal conditions of the loop and aborts the loop before the loop instructions are replayed.

13. A processor comprising:
a controller that detects a loop hint instruction characterizing a loop including a plurality of loop instructions, before any execution of the loop instructions occurs, wherein the loop hint instruction includes a loop iteration information specifying whether the loop is an indefinite loop or a definite loop, a definite loop count being specified for the definite loop and no definite loop count being specified for the indefinite loop;
an instruction queue that stores loop information including the loop hint instruction and the loop instructions; and
an execution unit that executes the loop instructions in a first iteration,
wherein a loop iteration is counted based on the loop information,
whether a last iteration of the loop instructions is completed is determined, and
the instruction queue replays the loop instructions for execution until the last iteration is completed,
wherein at least one of delay time and power consumption is reduced.

14. The processor of claim 13 , wherein the controller marks the loop instructions in the queue, based on the loop information.

15. The processor of claim 13 , wherein the loop hint instruction and the plurality of loop instructions are contained in fetch parcels obtained from a cache, and wherein the loop hint instruction further includes (i) a start instruction offset inside the loop's first fetch parcel, (ii) an end instruction offset inside the loop's last fetch parcel, and (iii) a total number of fetch parcels in the loop including the first and last fetch parcels.

16. A processor comprising:
a controller that identifies loop information corresponding to a plurality of loop instructions, before any execution of the loop instructions occurs;
a queue that stores the loop instructions; and
an execution unit that executes the loop instructions in a first iteration,
wherein a loop iteration is counted based on the identifie

Assignees

• Intel Corp

Inventors

• Lipshits Masha
• Rappaport Lihu
• Gupta Shantanu
• Sala Franck
• Kumar Naveen
• Knies Allan D

Classifications

• G06F9/3844

  using dynamic branch prediction, e.g. using branch history tables · CPC title

• G06F9/325

  for loops, e.g. loop detection or loop counter · CPC title

• G06F9/381

  Loop buffering · CPC title

• G06F9/30065 Primary

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title