Printed circuit board

Patent metadata

Field	Value
Publication number	US-10912194-B2
Application number	US-201916673813-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	Jul 31, 2018
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

Generally, the present disclosure provides example embodiments relating to a printed circuit board (PCB). In an embodiment, a structure includes a PCB including insulating layers with respective metal layers being disposed therebetween. Each of first layers of the insulating layers includes a first fiberglass content. A second layer of the insulating layers has a second fiberglass content less than the first fiberglass content. For example, in some embodiments, the second insulating layer does not include a fiberglass matrix.

First claim

What is claimed is:

1. A method comprising:
forming a printed circuit board (PCB) comprising:
coating a second insulating layer on a first insulating layer, the first insulating layer having a first fiberglass content, the first insulating layer on a third insulating layer without an intervening insulating layer between the first insulating layer and the third insulating layer, the third insulating layer including fiberglass, the second insulating layer having a second fiberglass content less than the first fiberglass content and the first insulating layer having a surface roughness that is greater than a surface roughness of the second insulating layer; and
joining a fourth insulating layer over the second insulating layer, the fourth insulating layer including fiberglass.

2. The method of claim 1 , wherein:
each of the first insulating layer, the third insulating layer and the fourth insulating layer is formed of pre-preg.

3. The method of claim 1 , wherein the second fiberglass content is substantially zero.

4. The method of claim 1 , wherein the second insulating layer is a resin layer.

5. The method of claim 1 , wherein the second insulating layer includes a filler material.

6. The method of claim 1 , further comprising:
depositing a first metal layer on the first insulating layer before coating the second insulating layer on the first insulating layer; and
depositing a second metal layer on the second insulating layer before joining the fourth insulating layer over the second insulating layer.

7. The method of claim 6 , wherein the first metal layer includes first metal lines, a first spacing and a first pitch being between neighboring pairs of the first metal lines; and
the second metal layer includes second metal lines, a second spacing and a second pitch being between neighboring pairs of the second metal lines, the first spacing being greater than the second spacing, the first pitch being greater than the second pitch.

8. The method of claim 7 , wherein a first width of a metal line in the first metal layer is greater than a second width of a metal line in the second metal layer.

9. The method of claim 7 , wherein a width of a metal line in the first metal layer is equal to or less than 10 μm.

10. The method of claim 7 , wherein a spacing between neighboring metal lines in the first metal layer is equal to or less than 10 μm.

11. A method comprising:
forming a printed circuit board (PCB) comprising:
coating a first insulating layer on a third insulating layer without an intervening insulating layer between the first insulating layer and the third insulating layer, the third insulating layer including fiberglass; and
coating a second insulating layer on the first insulating layer, the first insulating layer having a first fiberglass content, the second insulating layer having a second fiberglass content less than the first fiberglass content and the first insulating layer having a surface roughness that is greater than a surface roughness of the second insulating laver.

12. The method of claim 11 , further comprising depositing a second metal layer on the second insulating layer before joining a fourth insulating layer over the second insulating layer.

13. The method of claim 11 , further comprising depositing a first metal layer on the first insulating layer before coating the second insulating layer on the first insulating layer.

14. The method of claim 13 , wherein the second fiberglass content is substantially zero.

15. The method of claim 13 , wherein the second insulating layer includes a filler.

16. A method comprising:
forming a printed circuit board (PCB) comprising:
coating a second insulating layer on a first insulating layer and on a first metal layer, the first insulating layer having a first fiberglass content, the first metal layer being on the first insulating layer, the first insulating layer on a third insulating layer without an intervening insulating layer between the first insulating layer and the third insulating layer, the third insulating layer including fiberglass, the second insulating layer having a second fiberglass content less than the first fiberglass content and the first insulating layer having a surface roughness that is greater than a surface roughness of the second insulating layer; and
after coating the second insulating layer, depositing a second metal layer on the second insulating layer.

17. The method of claim 16 , wherein the first metal layer includes first metal lines, a first spacing and a first pitch being between neighboring pairs of the first metal lines; and
the second metal includes second metal lines, a second spacing and a second pitch being between neighboring pairs of the second metal lines, the first spacing being greater than the second spacing, the first pitch being greater than the second pitch.

18. The method of claim 17 , wherein a first width of a metal line in the first metal layer is greater than a second width of a metal line in the second metal layer.

19. The method of claim 17 , wherein a width of a metal line in the first metal layer is equal to or less than 10 μm.

20. The method of claim 17 , wherein a spacing between neighboring metal lines in the first metal layer is equal to or less than 10 μm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsao Pei-Haw
• Lu Tsung-Hsing
• Chu Li-Huan

Classifications

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H01B3/084 Primary

  Glass or glass wool in binder · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/635

  Through-vias · CPC title