Wiring substrate, semiconductor device, and method for manufacturing wiring substrate

Patent metadata

Field	Value
Publication number	US-9859201-B2
Application number	US-201514730743-A
Country	US
Kind code	B2
Filing date	Jun 4, 2015
Priority date	Jun 10, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.

First claim

The invention claimed is:

1. A wiring substrate comprising:
a first wiring structure; and
a second wiring structure stacked on an upper surface of the first wiring structure, wherein:
the first wiring structure includes
a first insulation layer, and
a via wiring that fills a first through hole extending through the first insulation layer in a thickness-wise direction, wherein the via wiring includes an upper end face exposed from an upper surface of the first insulation layer;

the second wiring structure includes
a first wiring layer formed on the upper surface of the first insulation layer and the upper end face of the via wiring,
a first plane layer stacked on the upper surface of the first insulation wherein the first plane layer is one of a power supply plane and a ground plane and is an at least partially grid-shaped conductive layer in a plan view to define second through holes extending through the first plane layer in the thickness-wise direction, wherein the partially grid-shaped conductive layer includes a seed layer and a plated metal layer; wherein a width of a top surface of the plated metal layer is greater than a width of the seed layer, and
a second insulation layer stacked on the upper surface of the first insulation layer, wherein the second insulation layer fills the second through holes and covers entire top and side surfaces of the first plane layer and entire top and side surfaces of the first wiring layer;

the second wiring structure has a higher wiring density than the first wiring structure; and
the second through holes each include an upper open end and a lower open end, wherein the upper open end has a smaller open width than the lower open end.

2. The wiring substrate according to claim 1 , wherein the top surface of the first plane layer is curved and upwardly bulged from a peripheral portion toward a central portion.

3. The wiring substrate according to claim 1 , wherein:
the second wiring structure further includes
a second wiring layer stacked on an upper surface of the second insulation layer and electrically connected to the first wiring layer,
a second plane layer stacked on the upper surface of the second insulation layer, wherein the second plane layer is at least partially grid-shaped in a plan view to define third through holes extending through the second plane layer in the thickness-wise direction, and
a third insulation layer stacked on the upper surface of the second insulation layer, wherein the third insulation layer fills the third through holes and covers the second plane layer and the second wiring layer;

the third through holes each include an upper open end and a lower open end, wherein the upper open end of each third through hole has a smaller open width than the lower open end of each third through hole; and
the first plane layer and the second plane layer are arranged at positions different from each other in a planar direction so that the second through holes of the first plane layer are located at positions different from the third through holes of the second plane layer in a plan view.

4. The wiring substrate according to claim 1 , wherein
the first wiring layer includes a seed layer formed on the upper end face of the via wiring, and
the upper surface of the first insulation layer is flush with the upper end face of the via wiring.

5. The wiring substrate according to claim 1 , wherein
the first wiring structure includes one or more insulation layers, each including a non-photosensitive resin as a main component; and
the second insulation layer of the second wiring structure includes a photosensitive resin as a main component and is thinner than each insulation layer of the first wiring structure.

6. The wiring substrate according to claim 1 , wherein the open width of the upper open end of each of the second through holes is set to be greater than a thickness of the second insulation layer formed on the first plane layer.

7. A semiconductor device comprising:
a wiring substrate; and
a semiconductor chip mounted on the wiring substrate;
wherein the wiring substrate includes
a first wiring structure, and
a second wiring structure stacked on an upper surface of the first wiring structure, wherein:
the first wiring structure includes
a first insulation layer, and
a via wiring that fills a first through hole extending through the first insulation layer in a thickness-wise direction, herein the via wiring includes an upper end face exposed from an upper surface of the first insulation layer;

the second wiring structure includes
a first wiring layer formed on the upper surface of the first insulation layer and the upper end face of the via wiring,
a first plane layer stacked on the upper surface of the first insulation layer, wherein the first plane layer is one of a power supply plane and a ground plane and is an at least partially grid-shaped conductive layer in a plan view to define second through holes extending through the first plane layer in the thickness-wise direction, wherein the partially grid-shaped conductive layer includes a seed layer and a plated metal layer, wherein a width of a top surface of the plated metal layer is greater than a width of the seed layer,
a second insulation layer stacked on the upper surface of the first insulation layer, wherein the second insulation layer fills the second through holes and covers entire top and side surfaces of the first plane layer and entire top and side surfaces of the first wiring layer, and
an uppermost wiring layer electrically connected to the first wiring layer, wherein the semiconductor chip is flip-chip-mounted on the uppermost wiring layer;

the second wiring structure has a higher wiring density than the first wiring structure; and
the second through holes each include an upper open end and a lower open end, wherein the upper open end has a smaller open width than the lower open end.

8. The wiring substrate according to claim 1 , wherein
the upper open end of each of the second through holes is located at a middle portion of the second insulation layer in the thickness-wise direction, and
the lower open end of each of the second through holes is located at a lower surface of the second insulation layer.

9. The semiconductor device according to claim 7 , wherein
the upper open end of each of the second through holes is located at a middle portion of the second insulation layer in the thickness-wise direction, and
the lower open end of each of the second through holes is located at a lower surface of the second insulation layer.

Assignees

• Shinko Electric Ind Co

Inventors

• Shimizu Noriyoshi
• Oi Kiyoshi
• Shimizu Yuichiro

Classifications

• H05K1/181

  associated with surface mounted components · CPC title

• H05K3/0055

  After-treatment, e.g. cleaning or desmearing of holes · CPC title

• H05K2201/0141

  Liquid crystal polymer [LCP] · CPC title

• H05K2203/061

  of previously made multilayered subassemblies · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title