Integrated circuit metallic ion diffusion defect validation

Patent metadata

Field	Value
Publication number	US-10910281-B2
Application number	US-201916256395-A
Country	US
Kind code	B2
Filing date	Jan 24, 2019
Priority date	Jan 24, 2019
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

A method for validating that an integrated circuit die is not susceptible to a conductive metallic ion diffusion defect is disclosed. A test component is applied to a backside surface of the integrated circuit die to form a test assembly. The test component includes a conductive metal layer and a transport media layer for facilitating diffusion of conductive metallic ions. The test assembly is heated at a thermal activation temperature. The integrated circuit die is computer validated to determine whether or not the integrated circuit die has the conductive metallic ion diffusion defect.

First claim

The invention claimed is:

1. A method for validating that an integrated circuit die is not susceptible to a conductive metallic ion diffusion defect, the method comprising:
applying a test component to a backside surface of the integrated circuit die to form a test assembly, wherein the test component includes a conductive metal layer and a transport media layer for facilitating diffusion of conductive metallic ions;
heating the test assembly at a thermal activation temperature; and
computer validating the integrated circuit die to determine whether or not the integrated circuit die has the conductive metallic ion diffusion defect.

2. The method of claim 1 , further comprising:
pressurizing the test assembly at an increased pressure relative to an ambient pressure while the test assembly is being heated.

3. The method of claim 2 , wherein the transport media includes adsorbed H 2 O.

4. The method of claim 1 , wherein the transport media includes a thermal interface material.

5. The method of claim 1 , wherein the conductive metal includes copper.

6. The method of claim 1 , wherein the test component covers substantially an entire backside surface of the integrated circuit die.

7. The method of claim 1 , wherein the test assembly further includes a heat sink, and wherein the heat sink is clamped to the integrated circuit die to compress the conductive metal layer and the transport media layer of the test component to the backside surface of the integrated circuit die.

8. The method of claim 1 , wherein the conductive metal layer is applied to the backside surface of the integrated circuit die, and wherein the transport media layer is applied to the conductive metal layer.

9. The method of claim 1 , wherein the transport media layer is applied to the backside surface of the integrated circuit die, and wherein the conductive metal layer is applied to the transport media layer.

10. The method of claim 1 , wherein the test assembly is heated for a designated duration that is selected from a temporal range of 72-120 hours.

11. The method of claim 1 , wherein the thermal activation temperature is selected from a thermal range of 100-150 degrees Celsius.

12. The method of claim 1 , wherein the transport media layer has a surface area greater than or equal to a surface area of the conductive metal layer.

13. The method of claim 1 , wherein computer validating includes installing the integrated circuit die in a test computing device, and determining that the integrated circuit die has the conductive metallic ion diffusion defect based on the test computing device not being able to be powered on.

14. The method of claim 1 , wherein computer validating includes installing the integrated circuit die in a test computing device, and determining that the integrated circuit die has the conductive metallic ion diffusion defect based on the test computing device producing rendered images having graphical artifacts.

15. The method of claim 1 , wherein computer validating includes performing a self-test of the integrated circuit die and determining that the integrated circuit die has the conductive metallic ion diffusion defect based on the self-test producing an expected result.

16. A method for validating that an integrated circuit die is not susceptible to a copper ion diffusion defect, the method comprising:
applying a test component to a backside surface of the integrated circuit die to form a test assembly, wherein the test component includes a copper layer and a thermal interface material layer for facilitating diffusion of copper ions;
heating the test assembly at a thermal activation temperature greater than an operating temperature of the integrated circuit die for a designated duration;
removing the test component from the integrated circuit die; and
computer validating the integrated circuit die to determine whether or not the integrated circuit die has the copper ion diffusion defect.

17. The method of claim 16 , wherein the test assembly further includes a heat sink, and wherein the heat sink is clamped to the integrated circuit die to compress the copper layer and the thermal interface material layer of the test component to the backside surface of the integrated circuit die.

18. The method of claim 16 , wherein the copper layer is applied to the backside surface of the integrated circuit die, and wherein the transport media layer is applied to the thermal interface material layer.

19. The method of claim 16 , wherein the thermal activation temperature is selected from a thermal range of 100-150 degrees Celsius and wherein the designated duration that the test assembly is heated is selected from a temporal range of 72-120 hours.

20. A method for validating that an integrated circuit die is not susceptible to a copper ion diffusion defect, the method comprising:
applying a test component to a backside surface of the integrated circuit die to form a test assembly, wherein the test component includes a copper layer and a transport media layer for facilitating diffusion of copper ions;
heating the test assembly at a thermal activation temperature greater than an operating temperature of the integrated circuit die for a designated duration;
pressurizing the test assembly at an increased pressure relative to an ambient pressure while the test assembly is being heated at the thermal activation temperature;
removing the test component from the integrated circuit die; and
computer validating the integrated circuit die to determine whether or not the integrated circuit die has the copper ion diffusion defect.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Mccormack Mark Thomas
• Kordus Ii Louis Charles
• Mehta Anik

Classifications

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G01N33/20

  Metals · CPC title

• H01L22/20

  Electricity · mapped topic