Array substrate and repairing method thereof, display panel

Patent metadata

Field	Value
Publication number	US-10908467-B2
Application number	US-201916522854-A
Country	US
Kind code	B2
Filing date	Jul 26, 2019
Priority date	Jul 27, 2018
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

The present disclosure provides an array substrate and a method for repairing the same, and a display panel. The array substrate includes gate lines extending in a first direction, and data lines and common electrode lines extending in a second direction. The gate lines intersect with the common electrode lines and the data lines to define pixel units. Every two adjacent pixel units at two sides of a common electrode line constitute a pixel unit group. Common electrodes of two pixel units in a pixel unit group are each connected to a common electrode line therebetween. The array substrate further includes a repairing structure including a first repairing line, a second repairing line at two sides of a data line, respectively, and a middle line intersecting with the data line and connecting a first point of the first repairing line and a second point of the second repairing line.

First claim

What is claimed is:

1. An array substrate, comprising a plurality of gate lines extending in a first direction, and a plurality of data lines and a plurality of common electrode lines extending in a second direction,
wherein the plurality of common electrode lines and the plurality of data lines are alternately arranged, the plurality of gate lines intersect with the plurality of common electrode lines and the plurality of data lines to define a plurality of pixel units, every two adjacent ones of the plurality of pixel units at two sides of one of the common electrode lines constitute a pixel unit group, and common electrodes of two pixel units of the plurality of pixel units in a same pixel unit group are each connected to a common electrode line between the two pixel units,
the array substrate further comprises a repairing structure between two adjacent pixel unit groups in the first direction and comprising a first repairing line, a second repairing line and a middle line, wherein the first repairing line and the second repairing line are at two sides of a data line of the plurality of data lines between the two pixel unit groups, respectively, the middle line intersects with the data line between the two pixel unit groups and connects a first point of the first repairing line and a second point of the second repairing line, the first repairing line is connected to a common electrode of a pixel unit of the plurality of pixel units adjacent to the repairing structure at a side of the repairing structure, and the second repairing line is connected to a common electrode of a pixel unit of the plurality of pixel units adjacent to the repairing structure at another side of the repairing structure.

2. The array substrate of claim 1 , wherein the repairing structure and the plurality of gate lines are in a same layer.

3. The array substrate of claim 1 , wherein the first repairing line and the second repairing line are parallel to the data line.

4. The array substrate of claim 3 , wherein the middle line connects a middle point of the first repairing line and a middle point of the second repairing line.

5. The array substrate of claim 1 , wherein each pixel unit group comprises a first pixel unit and a second pixel unit, the first pixel unit comprises a first thin film transistor, the second pixel unit comprises a second thin film transistor, and a source electrode of the first thin film transistor and a source electrode of the second thin film transistor in a same pixel unit group are connected to a same data line.

6. The array substrate of claim 5 , wherein in a same pixel unit group, a drain electrode of the first thin film transistor is connected to a pixel electrode of the first pixel unit; a drain electrode of the second thin film transistor is connected to a pixel electrode of the second pixel unit through a conductive line, and the second thin film transistor and the conductive line are not covered by any common electrode of the pixel unit group.

7. The array substrate of claim 6 , wherein the conductive line comprises a connection electrode in a same layer with the common electrode and a metal connection line in a same layer with the data line.

8. The array substrate of claim 5 , wherein the first pixel unit and the second pixel unit in a same pixel unit group share one common electrode.

9. The array substrate of claim 5 , wherein the first pixel unit and the second pixel unit in a same pixel unit group are connected to two gate lines of the plurality of gate lines at two sides of the pixel unit group, respectively.

10. A method for repairing an array substrate, wherein the array substrate comprises a plurality of gate lines extending in a first direction, and a plurality of data lines and a plurality of common electrode lines extending in a second direction, the plurality of common electrode lines and the plurality of data lines are alternately arranged, the plurality of gate lines intersect with the plurality of common electrode lines and the plurality of data lines to define a plurality of pixel units, every two adjacent ones of the plurality of pixel units at two sides of one of the common electrode lines constitute a pixel unit group, and common electrodes of two pixel units of the plurality of pixel units in a same pixel unit group are each connected to a common electrode line between the two pixel units, the array substrate further comprises a repairing structure between two adjacent pixel unit groups in the first direction and comprising a first repairing line, a second repairing line and a middle line, wherein the first repairing line and the second repairing line are at two sides of a data line of the plurality of data lines between the two pixel unit groups, respectively, the middle line intersects with the data line between the two pixel unit groups and connects a first point of the first repairing line and a second point of the second repairing line, the first repairing line is connected to a common electrode of a pixel unit of the plurality of pixel units adjacent to the repairing structure at a side of the repairing structure, and the second repairing line is connected to a common electrode of a pixel unit of the plurality of pixel units adjacent to the repairing structure at another side of the repairing structure, and the method comprises:
in a case where at least one of the gate lines and the data lines has a disconnection point, performing a cutting process on at least one of the repairing structure, a common electrode of a pixel unit and a common electrode line, which are adjacent to the disconnection point, such that a signal supposed to be transmitted through the disconnection point is transmitted through at least one of the repairing structure, the common electrode and the common electrode line and bypasses the disconnection point.

11. The method of claim 10 , wherein in a case where the data line has a first disconnection point between middle lines of two adjacent repairing structures, the method comprises:
for each of the two adjacent repairing structures at two sides of the first disconnection point, performing a cutting process at the second point to disconnect the second repairing line and the middle line;
for each of the two adjacent repairing structures, performing a cutting process on the first repairing line, a common electrode of the pixel unit connected to the first repairing line and a common electrode line of the pixel unit, from a third point of the first repairing line on a side of the first point away from the first disconnection point to an edge of the pixel unit close to the other repairing structure of the two adjacent repairing structures; and
electrically connecting both of the middle lines of the two adjacent repairing structures at the two sides of the first disconnection point with the data line.

12. The method of claim 10 , wherein each pixel unit group comprises a first pixel unit and a second pixel unit, the first pixel unit comprises a first thin film transistor, the second pixel unit comprises a second thin film transistor, a source electrode of the first thin film transistor and a source electrode of the second thin film transistor in a same pixel unit group are connected to a same data line, and a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor in a same pixel group are connected to two of the plurality of gate lines at two sides of the pixel unit group, respectively,
in a case where a gate line connected to the second pixel unit has a second disconnection point between two second pixel units, the method comprises:
for each of two common electrode lines at two sides of the sec

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Hu Lang
• Li Kaiqiang
• Yu Yang
• Wang Chaolei
• Rong Nannan
• Jiang Yaohua
• Wu Qiulin
• Zhang Baohao

Classifications

• G02F1/1309 Primary

  Repairing; Testing · CPC title

• G02F1/136272

  Auxiliary lines · CPC title

• G02F1/136259 Primary

  Repairing; Defects · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title