Array substrate, method of repairing the same, display panel and display device

US9678399B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9678399-B2
Application numberUS-201615139651-A
CountryUS
Kind codeB2
Filing dateApr 27, 2016
Priority dateAug 3, 2015
Publication dateJun 13, 2017
Grant dateJun 13, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An array substrate, a method of repairing the same, a display panel and a display device are disclosed. A data-line repair line, which is connected with a data line and insulated from a common electrode, is provided in each pixel area in an array substrate and an orthogonal projection of the data-line repair line on a base substrate has an overlapped area with an orthogonal projection of a sub-electrode or a connection line of a common electrode on the substrate. Therefore, if a breakage occurs to a data line at its overlapped area with a gate line on the array substrate, it is able to repair the breakage via the date line repair line and a portion cut out of the common electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. An array substrate, comprising: a base substrate; gate lines and data lines that are arranged in a cross manner on the base substrate and a common electrode, wherein the common electrode comprises: sub-electrodes each in pixel areas defined by the gate lines and the data lines, common electrode lines that extend in a same direction as the gate lines and are employed to transmit a common electrode signal to the sub-electrodes, and connection lines that each electrically connects two sub-electrodes that are adjacent to each other in a direction along which the data lines extend; and data-line repair lines that are connected with the data lines and insulated from the common electrode within the pixel areas, wherein an orthogonal projection of the data-line repair lines on the base substrate has an overlapped area with an orthogonal projection of the sub-electrodes or the connection lines on the base substrate. 2. The array substrate according to claim 1 , wherein the orthogonal projection of the data-line repair lines on the base substrate does not overlap with an orthogonal projection of the common electrode lines on the base substrate. 3. The array substrate according to claim 2 , wherein the common electrode lines are provided on a side of the sub-electrodes and the data-line repair lines are provided between the gate lines, which are adjacent to and have a greater distance to the common electrode lines, and the common electrode lines. 4. The array substrate according to claim 3 , wherein the data-line repair lines provided between the gate lines and the common electrode lines is disposed on a side closer to the gate lines. 5. The array substrate according to claim 2 , wherein the data-line repair lines are in parallel with the common electrode lines within the pixel areas that the data-line repair lines belong to respectively. 6. The array substrate according to claim 1 , wherein the connection lines are in parallel with the data lines. 7. The array substrate according to claim 6 , wherein the data-line repair lines are provided on a side of the data lines, on which side the data lines to which the data-line repair lines are electrically connected respectively are closer to adjacent connection lines. 8. The array substrate according to claim 1 , wherein the data-line repair lines are provided on a same layer and formed of a same material as the data lines. 9. The array substrate according to claim 8 , wherein the data-line repair lines are directly electrically connected with the data lines. 10. The array substrate according to claim 1 , further comprising pixel electrodes that are provided on the base substrate and insulated from the common electrode, wherein the connection lines are provided on a same layer and formed of a same material as the pixel electrodes and the connection lines are electrically connected to corresponding sub-electrodes by means of via holes. 11. The array substrate according to claim 2 , wherein the data-line repair lines are provided on a same layer and formed of a same material as the data lines. 12. The array substrate according to claim 11 , wherein the data-line repair lines are directly electrically connected with the data lines. 13. The array substrate according to claim 2 , further comprising pixel electrodes that are provided on the base substrate and insulated from the common electrode, wherein the connection lines are provided on a same layer and formed of a same material as the pixel electrodes and the connection lines are electrically connected to corresponding sub-electrodes by means of via holes. 14. The array substrate according to claim 3 , wherein the data-line repair lines are provided on a same layer and formed of a same material as the data lines. 15. The array substrate according to claim 14 , wherein the data-line repair lines are directly electrically connected with the data lines. 16. The array substrate according to claim 3 , further comprising pixel electrodes that are provided on the base substrate and insulated from the common electrode, wherein the connection lines are provided on a same layer and formed of a same material as the pixel electrodes and the connection lines are electrically connected to corresponding sub-electrodes by means of via holes. 17. A display panel, comprising the array substrate according to claim 1 . 18. A display device, comprising the display panel according to claim 17 . 19. A method of repairing the array substrate according to claim 1 , comprising: determining a breakage position of a data line where an open circuit occurs on the array substrate; determining a common electrode line that is closer to the breakage position on two sides of the breakage position, and determining a data-line repair line that is closer to the breakage position and electrically connected with the data line suffering from the open circuit; as to the determined common electrode line, selecting a welding point at an overlapped area between the common electrode line and the data line, and employing a laser welding process to electrically connect the common electrode line and the data line at the welding point; as to the determined data-line repair line, selecting a welding point at an overlapped area between the data-line repair line and a sub-electrode or at an overlapped area between the data-line repair line and a connection line, and employing a laser welding process to electrically connect the sub-electrode or the connection line at the welding point with the data-line repair line; and cutting the common electrode according to the common electrode line and the data-line repair line determined to allow a portion cut out of the common electrode to be insulated from a rest portion and allow the portion cut out of the common electrode to electrically connect two ends to the breakage position of the data line.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9678399B2 cover?
An array substrate, a method of repairing the same, a display panel and a display device are disclosed. A data-line repair line, which is connected with a data line and insulated from a common electrode, is provided in each pixel area in an array substrate and an orthogonal projection of the data-line repair line on a base substrate has an overlapped area with an orthogonal projection of a sub-…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/136259. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 13 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).