Array substrate and repairing method thereof, testing method thereof, manufacturing method thereof, display device

Patent metadata

Field	Value
Publication number	US-2016358524-A1
Application number	US-201615096706-A
Country	US
Kind code	A1
Filing date	Apr 12, 2016
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

An array substrate provided by embodiments of the present disclosure may include: a base substrate; a gate line pattern and a data line pattern formed on the base substrate; a gate insulating layer pattern formed between the gate line pattern and the data line pattern; and a spare line pattern formed on a same layer as the gate line pattern. The spare line pattern may include a plurality of spare lines which are substantially in parallel with the gate lines in the gate line pattern. Respective spare lines may be arranged at a plurality of rows of pixels defined by the gate line pattern and the data line pattern. And the respective spare lines and respective data lines in the data line pattern may have respective vertically overlapped regions. The array substrate and a repairing method thereof provided by embodiments of the present disclosure may repair a data line disconnection defect rapidly when the defect occurs in the array substrate. In addition, the repairing process is relatively simple and is easy to be implemented.

First claim

What is claimed is:

1 . An array substrate, comprising:
a base substrate; a gate line pattern and a data line pattern formed on the base substrate; a gate insulating layer pattern formed between the gate line pattern and the data line pattern; and a spare line pattern formed on a same layer as the gate line pattern, wherein the spare line pattern comprises a plurality of spare lines which are substantially in parallel with the gate lines in the gate line pattern, respective spare lines are arranged at a plurality of rows of pixels defined by the gate line pattern and the data line pattern, and the respective spare lines and respective data lines in the data line pattern have respective vertically overlapped regions.

2 . The array substrate of claim 1 , wherein each of the spare lines is arranged at each of the plurality of rows of pixels defined by the gate line pattern and the data line pattern.

3 . The array substrate of claim 1 , wherein the gate insulating layer pattern is formed over the gate line pattern and the spare line pattern, and the data line pattern is formed on the gate insulating layer pattern;
the array substrate further comprises: a pixel electrode pattern formed on the gate insulating layer pattern; the pixel electrode pattern comprises pixel electrode blocks corresponding to respective pixels, a passivation layer pattern formed over the pixel electrode pattern, and a common electrode pattern formed over the passivation layer pattern; the respective spare lines in the spare line pattern and respective pixel electrode blocks located over the respective spare lines have respective vertically overlapped regions, and tooling holes are formed within the respective vertical overlapped regions on the passivation layer pattern; and the respective spare lines in the spare line pattern extend to a bezel region of the array substrate and are exposed at the bezel region.

4 . The array substrate of claim 3 , further comprising: an isolated electrode pattern formed over the passivation layer pattern,
wherein respective isolated electrodes in the isolated electrode pattern are isolated from common electrodes in the common electrode pattern, and are connected to the respective pixel electrodes in the pixel electrode pattern via respective tooling holes in the passivation layer pattern.

5 . The array substrate of claim 3 , wherein the spare lines in the spare line pattern each comprises a spare line main body and a conductive strip connected to the spare line main body, the conductive strip being located at the bezel region and being exposed at the bezel region.

6 . A method of repairing the array substrate according to claim 1 , wherein
when one data line in the array substrate is disconnected and is required to be repaired, the gate insulating layer at a vertically overlapped region between a segment of data line of the disconnected data line which is not connected to a data driven circuit and a spare line which has a vertically overlapped region with the segment of data line and is closest to the data driven circuit is melted, and the gate insulating layer at a vertically overlapped region between the spare line and one data line which is adjacent to the disconnected data line is melted, so that the segment of data line is connected to the adjacent data line via the spare line.

7 . The method of claim 6 , wherein
when one data line and one gate line are short-circuited, the data line is melted from a short circuit point, so that the data line is divided into two segments which are not connected to the gate line, and the two segments are processed according to processing steps performed when the data line is disconnected.

8 . A method of testing the array substrate according to claim 3 , wherein
when one pixel in the array substrate is required to be tested, gate insulating layer material at the tooling hole of the pixel is melted, so that the pixel electrode at the tooling hole of the pixel is connected to the spare line under the pixel electrode.

9 . A method for manufacturing an array substrate, the array substrate comprising: a base substrate; a gate line pattern and a data line pattern formed on the base substrate; a gate insulating layer pattern formed between the gate line pattern and the data line pattern; and a spare line pattern formed in a same layer as the gate line pattern,
the method comprising: forming the gate line pattern and the data line pattern on the base substrate, and the gate insulating layer pattern between the gate line pattern and the data line pattern; and forming the spare line pattern on a same layer as the gate line pattern, wherein the spare line pattern comprises a plurality of spare lines which are substantially in parallel with the gate lines in the gate line pattern, respective spare lines are arranged at a plurality of rows of pixels defined by the gate line pattern and the data line pattern, and the respective spare lines and respective data lines in the data line pattern have respective vertically overlapped regions.

10 . The method of claim 9 , wherein the step of forming the spare line pattern on the same layer as the gate line pattern comprises: forming the spare line pattern by a same process as that of forming the gate line pattern.

11 . The method of claim 9 , wherein when the array substrate is the array substrate according to claim 4 , the method further comprises:
forming the isolated electrode pattern by a same process as that of forming the common electrode pattern.

12 . A display device comprising an array substrate, the array substrate comprising:
a base substrate; a gate line pattern and a data line pattern formed on the base substrate; a gate insulating layer pattern formed between the gate line pattern and the data line pattern; and a spare line pattern formed on a same layer as the gate line pattern, wherein the spare line pattern comprises a plurality of spare lines which are substantially in parallel with the gate lines in the gate line pattern, respective spare lines are arranged at a plurality of rows of pixels defined by the gate line pattern and the data line pattern, and the respective spare lines and respective data lines in the data line pattern have respective vertically overlapped regions.

13 . The display device of claim 12 , wherein each of the spare lines is arranged at each of the plurality of rows of pixels defined by the gate line pattern and the data line pattern.

14 . The display device of claim 12 , wherein the gate insulating layer pattern is formed over the gate line pattern and the spare line pattern, and the data line pattern is formed on the gate insulating layer pattern;
the array substrate further comprises: a pixel electrode pattern formed on the gate insulating layer pattern; the pixel electrode pattern comprises pixel electrode blocks corresponding to respective pixels, a passivation layer pattern formed over the pixel electrode pattern, and a common electrode pattern formed over the passivation layer pattern; the respective spare lines in the spare line pattern and respective pixel electrode blocks located over the respective spare lines have respective vertically overlapped regions, and tooling holes are formed within the respective vertical overlapped regions on the passivation layer pattern; and the respective spare lines in the spare line pattern extend to a bezel region of the array substrate and are exposed at the bezel region.

15 . The display device of claim 14 , further comprising: an isolated electrode pattern formed over the passivation layer pattern,
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Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Feng Wei

Classifications

• H10W20/068

  by using a laser, e.g. laser cutting or laser direct writing · CPC title

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G02F2201/506

  Repairing, e.g. with redundant arrangement against defective part · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G02F1/136259 Primary

  Repairing; Defects · CPC title