Three dimensional vertically structured MISFET/MESFET

Patent metadata

Field	Value
Publication number	US-10903371-B2
Application number	US-201614990561-A
Country	US
Kind code	B2
Filing date	Jan 7, 2016
Priority date	Jan 7, 2016
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

First claim

What is claimed is:

1. An apparatus, comprising:
a substrate comprising a semiconductor material;
an array of three dimensional (3D) structures above the substrate, wherein each 3D structure comprises the semiconductor material, and wherein each 3D structure is a contiguous structure having only one conductivity type, wherein a ratio of a greatest height of each 3D structure to a width thereof is greater than 1:1;
an insulating barrier layer coupled to a portion of at least one vertical sidewall of each 3D structure;
a gate region having an inner surface formed on a portion of at least one vertical sidewall of each insulating barrier layer, the insulating barrier layer separating the inner surface of the gate region from the associated 3D structure, wherein a cavity region is defined between outer surfaces of the gate regions, wherein the cavity region separates the gate regions;
a source region formed directly on each 3D structure, the source region having at least one material directly adjacent the associated 3D structure, the material selected from the group consisting of a metal and a conductive oxide; and
a drain region below the substrate.

2. The apparatus as recited in claim 1 , wherein the conductivity type corresponds to an n-type conductivity or a p-type conductivity.

3. The apparatus as recited in claim 1 , wherein the semiconductor material is selected from the group consisting of: silicon, silicon carbide, a binary III-V semiconductor material, a ternary III-V semiconductor material, a quaternary III-V semiconductor material, and combinations thereof.

4. An apparatus, comprising:
a substrate comprising a semiconductor material;
at least one three dimensional (3D) structure above the substrate, wherein the 3D structure comprises the semiconductor material, wherein the semiconductor material comprises GaN, and wherein the 3D structure comprises a region having a conductivity type, wherein a ratio of a greatest height of the 3D structure to a width of the 3D structure is greater than 1:1, wherein the greatest height of the 3D structure is in a range from about 0.2 μm to about 1000 μm;
an insulating barrier layer coupled to a portion of at least one vertical sidewall of the 3D structure, wherein a total height of the insulating barrier layer is in a range of greater than 0% to less than or equal to a 100% of the total height of the 3D structure;
a gate region formed on a portion of at least one vertical sidewall of the insulating barrier layer, the insulating barrier layer separating the gate region from the 3D structure;
a source region formed directly on the 3D structure; and
a drain region below the substrate.

5. The apparatus as recited in claim 1 , wherein a total height of each 3D structure is in a range from about 0.1 μm to about 1000 μm.

6. The apparatus as recited in claim 1 , wherein a total width of each 3D structure is in a range from about 0.001 μm to about 100 μm.

7. The apparatus as recited in claim 1 , wherein each 3D structure is a pillar.

8. The apparatus as recited in claim 1 , wherein the insulating barrier layer surrounds the periphery of each 3D structure.

9. The apparatus as recited in claim 8 , wherein a total height of the insulating barrier layer is in a range from greater than 0% to less than or equal to 100% of a total height of each 3D structure.

10. The apparatus as recited in claim 1 , comprising an isolation region below the insulating barrier layer.

11. The apparatus as recited in claim 4 , comprising an array of 3D structures, wherein each 3D structure comprises the semiconductor material, and wherein each 3D structure has only one conductivity type, wherein an aspect ratio of each 3D structure is greater than 1:1.

12. The apparatus as recited in claim 1 ,
wherein the source region extends along an upper surface of each 3D structure; and
the drain region is formed below a lower surface of the substrate.

13. The apparatus as recited in claim 1 , wherein the insulating barrier layer comprises multiple insulating barrier layers.

14. The apparatus as recited in claim 13 , wherein each insulating barrier layer individually comprises at least one of: a polymeric material, glass, SiNx, SiO 2 , Al 2 O 3 , Ga 2 O 3 , MgO, Y 2 O 3 , Gd 2 O 3 , air, and combinations thereof.

15. The apparatus as recited in claim 13 , wherein a total height of the insulating barrier layer is in a range from greater than 0% to less than or equal to 100% of a total height of each 3D structure.

16. The apparatus as recited in claim 15 , wherein a length of the gate region measured vertically along the at least one vertical sidewall of the insulating barrier layer is greater than a thickness of a contiguous portion of the gate region measured horizontally in a direction away from the vertical sidewall of the insulating barrier layer that is adjacent the contiguous portion of the gate region.

17. The apparatus as recited in claim 16 , wherein a total height of the gate region is in a range from greater than 0% to less than or equal to 100% of the total height of the insulating barrier layer.

18. The apparatus as recited in claim 17 , comprising an isolation region below the gate region, wherein the isolation region completely fills a cavity region between each 3D structure.

19. The apparatus as recited in claim 18 , wherein the isolation region comprises at least one of: a polymeric material, glass, SiNx, SiO 2 , Al 2 O 3 , Ga 2 O 3 , MgO, Y 2 O 3 , Gd 2 O 3 , air, and combinations thereof.

20. The apparatus as recited in claim 1 , wherein an aspect ratio of the greatest height of each 3D structure to a greatest width of each 3D structure is greater than 1:1.

21. The apparatus as recited in claim 1 , wherein the width of each 3D structure is in a range of about 600 nm to about 100 μm.

22. The apparatus as recited in claim 1 , wherein a p-type or n-type dopant concentration of each 3D structure is in a range of about 2×10 17 cm −3 to about 1×10 19 cm −3 .

23. The apparatus as recited in claim 1 , wherein the 3D structures are arranged in a hexagonally close-packed array.

24. An apparatus, comprising:
a substrate comprising a semiconductor material;
an array of contiguous three dimensional (3D) structures above the substrate, wherein each 3D structure comprises the semiconductor material, and wherein each 3D structure has only one conductivity type;
an insulating barrier layer coupled to a portion of at least one vertical sidewall of the 3D structure;
a gate region formed on a portion of at least one vertical sidewall of the insulating barrier layer, the insulating barrier layer separating the gate region from the 3D structure;
an isolation region completely filling a cavity region between each 3D structure; and
a source region formed directly above the 3D structure, the source region having at least one material directly adjacent the 3D structure selected from the group consisting of a metal and a conductive oxide; and
a drain region below the substrate.

Assignees

• L Livermore Nat Security Llc
• Univ California

Inventors

• Conway Adam
• Harrison Sara Elizabeth
• Nikolic Rebecca J
• Shao Qinghui
• Voss Lars
• Chowdhury Srabanti

Classifications

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title