Electronic Devices Including A III-V Transistor Having A Homostructure And A Process Of Forming The Same

Patent metadata

Field	Value
Publication number	US-2016308045-A1
Application number	US-201514690703-A
Country	US
Kind code	A1
Filing date	Apr 20, 2015
Priority date	Apr 20, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be disposed between a first portion and a second portion of the gate electrode. In an embodiment, the III-V transistor can be an enhancement-mode GaN transistor, and in a particular embodiment, the drain, source, and channel regions can include the same conductivity type.

First claim

1 . An electronic device comprising a vertical III-V transistor comprising:
a gate electrode; a heavily-doped drain region; a voltage blocking layer; and a channel region within a homostructure, wherein:
the channel region is disposed between a first portion and a second portion of the gate electrode; and
the voltage blocking layer is disposed between the channel region and the heavily-doped drain region.

2 . The electronic device of claim 1 , wherein the vertical III-V transistor is an enhancement-mode transistor.

3 . The electronic device of claim 2 , wherein the vertical III-V transistor further comprises a source region, wherein the channel region is disposed between the heavily-doped drain and source region, and wherein the heavily-doped drain region, source region, and the channel region have a same conductivity type.

4 . The electronic device of claim 3 , wherein the same conductivity type is an n-type conductivity.

5 . The electronic device of claim 3 , wherein the same conductivity type is a p-type conductivity.

6 . The electronic device of claim 1 , wherein the vertical III-V transistor further comprises a cavity is disposed between the gate electrode and the heavily-doped drain region and lies adjacent to the voltage blocking layer.

7 . The electronic device of claim 1 , wherein the voltage blocking layer is disposed between a first portion and a second portion of a cavity.

8 . The electronic device of claim 1 , wherein the gate electrode surrounds portions of the source region and the voltage blocking layer, and does not surround any part of the heavily-doped drain region.

9 . (canceled)

10 . The electronic device of claim 1 , wherein the III-V transistor is a GaN transistor.

11 . The electronic device of claim 10 , wherein the GaN transistor further comprises a source region, wherein:
the source region, the channel region, the voltage blocking layer, and the heavily-doped drain region have a same conductivity type; the channel region is disposed between the source region and the voltage blocking layer and has a dopant concentration no greater than 1×10 15 atoms/cm 3 ; the voltage blocking layer has a dopant concentration in a range of 5×10 16 atoms/cm 3 to 5×10 18 atoms/cm 3 .

12 . A process of forming an electronic device comprising:
forming a patterned homostructure including a first heavily-doped layer, a channel layer, and a second heavily-doped layer, wherein a first opening extends through all of a thickness of each of the second heavily-doped layer and the channel layer; forming a gate electrode layer within the first opening; and etching a portion of the gate electrode layer to form and recess a gate electrode within the first opening, wherein a channel region is disposed between a first portion and a second portion of the gate electrode, wherein the first heavily-doped layer, the channel layer, the second heavily-doped layer, and the gate electrode are parts of a vertical III-V transistor.

13 . (canceled)

14 . The process of claim 12 , wherein forming the gate electrode layer comprises:
forming a first conductive film of the gate electrode; and forming a second conductive film that is a bulk conductive film for the gate electrode, wherein the first and second conductive films have different compositions.

15 . The process of claim 12 , further comprising providing a substrate that includes the first heavily-doped layer, a voltage blocking layer, the channel layer, and the second heavily-doped layer, wherein the voltage blocking layer is disposed between the first heavily-doped layer and the channel layer, and the channel layer is disposed between the voltage blocking layer and the second heavily-doped layer.

16 . The process of claim 15 , wherein the first opening extends through at least most of the voltage blocking layer.

17 . The process of claim 15 , further comprising:
forming a sacrificial layer within the first opening before forming the gate electrode; and removing the sacrificial layer from the first opening after forming the gate electrode to define a cavity adjacent to the voltage blocking layer.

18 . The process of claim 12 , wherein the first heavily-doped layer, the channel layer, and the second heavily-doped layer have a same conductivity type.

19 . The process of claim 18 , wherein the vertical III-V transistor is an enhancement-mode transistor.

20 . The process of claim 12 , further comprising:
providing a substrate that includes a base material, the first heavily-doped layer, the channel layer, a voltage blocking layer, and the second heavily-doped layer, wherein the channel layer is disposed between the voltage blocking layer and the second heavily-doped layer; patterning the base material to define a second opening that expose a portion of the first heavily-doped layer; and forming a conductive layer with within the second opening and contacting the first heavily-doped layer.

21 . The electronic device of claim 1 , wherein the gate electrode includes a lower conductive film and a bulk conductive film, wherein the lower conductive film laterally surrounds and underlies the bulk conductive film.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Moens Peter
• Vanmeerbeek Piet
• Parsey Jr John Michael

Classifications

• H10D64/01358

  the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title