Semiconductor device with released source and drain

Patent metadata

Field	Value
Publication number	US-10903364-B2
Application number	US-201616304620-A
Country	US
Kind code	B2
Filing date	Jul 2, 2016
Priority date	Jul 2, 2016
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate channel below a gate contact for the device;
a source/drain channel below source/drain portions of the device; and
one or more metal contacts surrounding the source/drain channel;
wherein the one or more metal contacts are formed surrounding the source/drain channel in one or more cavities etched around the source/drain channel.

2. The device of claim 1 , wherein the one or more metal contacts are wrap around contacts for the source/drain channel that provide contact with all sides of the source/drain.

3. The device of claim 1 , further comprising a buffer layer formed below the gate channel and the source/drain channel.

4. The device of claim 3 , wherein the buffer layer is a first III-V semiconductor material and the channel layer is a second III-V semiconductor material.

5. The device of claim 4 , wherein the channel layer comprises indium gallium arsenide (InGaAs).

6. The device of claim 4 , wherein the buffer layer comprises gallium arsenide (GaAs).

7. The device of claim 1 , wherein the semiconductor device is one of a trigate transistor or a nanowire device.

8. A system comprising:
one or more processors to process data;
a transmitter or receiver and antenna for transmission or reception of data; and
one or more semiconductor devices, a first semiconductor device including:
a gate channel below a gate contact for the device;
a source/drain channel below source/drain portions of the device; and
one or more metal contacts surrounding the source/drain channel;
wherein the one or more metal contacts are formed around the source/drain channel in one or more cavities etched around the source/drain channel.

9. The system of claim 8 , wherein the one or more metal contacts are wrap around contacts for the source/drain channel that provide contact with all sides of the source/drain of the first semiconductor device.

10. The system of claim 8 , wherein the first semiconductor device is one of a trigate transistor or a nanowire device.

Assignees

• Intel Corp

Inventors

• Rachmady Willy
• Gardner Sanaz K
• Mohapatra Chandra S
• Metz Matthew V
• Dewey Gilbert
• Ma Sean T
• Kavalieros Jack T
• Murthy Anand S
• Ghani Tahir

Classifications

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title