Double gate transistor device and method of operating

Patent metadata

Field	Value
Publication number	US-10903353-B2
Application number	US-201916293011-A
Country	US
Kind code	B2
Filing date	Mar 5, 2019
Priority date	Feb 29, 2016
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

First claim

What is claimed is:

1. A method comprising:
switching off a transistor device by interrupting a first conducting channel in a body region by driving a first gate electrode and, after interrupting the first conducting channel, interrupting a second conducting channel in the body region by driving a second gate electrode,
wherein the first gate electrode is dielectrically insulated from the body region by a first gate dielectric,
wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer,
wherein the body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region,
wherein driving the first gate electrode comprises decreasing a first drive voltage between the first gate electrode and the source region from a first on-level to a first off-level,
wherein driving the second gate electrode comprises decreasing a second drive voltage between the second gate electrode and the source region from a second on-level to a second off-level,
wherein the second off-level is different from the first off-level, and wherein driving the first gate electrode and the second gate electrode comprises decreasing the second drive voltage faster than the first drive voltage.

2. The method of claim 1 , wherein driving the first gate electrode comprises clamping the second gate electrode to the second on-level.

3. The method of claim 1 , further comprising:
detecting a change in an operation state of the transistor device,
wherein detecting the operation state comprises monitoring at least one electrical parameter of the second gate electrode.

4. The method of claim 3 , wherein monitoring the at least one electrical parameter of the second gate electrode comprises monitoring at least one of an electrical potential and a current to or from the second gate electrode.

5. The method of claim 4 , wherein monitoring the at least one electrical parameter comprises:
filtering a signal representing the current to or from the second gate electrode to obtain a filter signal; and
comparing the filter signal with a threshold.

6. The method of claim 5 , wherein detecting the change of the operation state comprises detecting the change in the operation state when the filter signal reaches the threshold.

7. The method of claim 3 , wherein driving the first gate electrode further comprises driving the first gate electrode based on a detected change of the operation state.

8. The method of claim 7 , wherein driving the first gate electrode based on the detected change of the operation state comprises:
driving the first gate electrode in accordance with a first drive parameter before the change of the operation state has been detected; and
driving the first gate electrode in accordance with a second drive parameter different from the first drive parameter after the change of the operation state has been detected.

9. The method of claim 8 , wherein the first drive parameter comprises a first current level of a drive current into the first gate electrode and the second drive parameter comprises a second current level of the drive current higher than the first current level.

10. The method of claim 1 , wherein the second gate electrode is positioned closer to the drift region of the transistor device than the first gate electrode.

11. The method of claim 1 , further comprising switching on the transistor device by generating the first conducting channel in the body region by driving the first gate electrode to a on voltage, and, after interrupting the first conducting channel, generating the second conducting channel in the body region by driving the second gate electrode to a second on voltage.

12. A method comprising:
switching off a transistor device by interrupting a first conducting channel in a body region by driving a first gate electrode and, after interrupting the first conducting channel, interrupting a second conducting channel in the body region by driving a second gate electrode,
wherein the first gate electrode is dielectrically insulated from the body region by a first gate dielectric,
wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer, and
wherein the body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region
wherein driving the first gate electrode comprises decreasing a first drive voltage between the first gate electrode and the source region from a first on-level to a first off-level according to a first slope,
wherein driving the second gate electrode comprises decreasing a second drive voltage between the second gate electrode and the source region from a second on-level to a second off-level according to a second slope, wherein the second slope is greater than the first slope, and
wherein the second off-level is different from the first off-level.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Bina Markus
• Mauder Anton
• Barrenscheen Jens

Classifications

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title