Integrated circuit packages

Patent metadata

Field	Value
Publication number	US-10903166-B2
Application number	US-201616060918-A
Country	US
Kind code	B2
Filing date	Jan 28, 2016
Priority date	Jan 28, 2016
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

First claim

The invention claimed is:

1. An integrated circuit (IC) package, comprising:
a die;
a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects;
a solder resist layer; and
second-level interconnects coupled to the redistribution structure through openings in the solder resist layer, wherein the second-level interconnects include solder at least partially in the openings in the solder resist layer, bottoms of the openings are provided by metal of the redistribution structure, and a surface of the solder resist layer is coplanar with the bottoms of the openings.

2. The IC package of claim 1 , wherein the solder resist layer is photoimageable.

3. The IC package of claim 1 , wherein the first-level interconnects include copper pillars.

4. The IC package of claim 1 , wherein the redistribution structure includes multiple redistribution layers, and the multiple redistribution layers include solder resist.

5. The IC package of claim 1 , wherein the second-level interconnects include solder balls.

6. The IC package of claim 1 , wherein the second-level interconnects include solder paste contacts.

7. A computing assembly, comprising:
a substrate; and
an integrated circuit (IC) package coupled to the substrate, wherein the IC package includes:
a die,
a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects,
a solder resist layer, and
second-level interconnects coupled to the redistribution structure through openings in the solder resist, wherein the openings in the solder resist layer are tapered such that the openings are narrower closer to the die, bottoms of the openings are provided by metal in a redistribution layer of the redistribution structure, and an interface between the solder resist layer and the redistribution layer is coplanar with the bottoms of the openings.

8. The computing assembly of claim 7 , wherein the die includes a processing device.

9. The computing assembly of claim 8 , wherein the die further includes a memory device.

10. The computing assembly of claim 7 , wherein the substrate is a printed circuit board (PCB).

11. The computing assembly of claim 7 , wherein the substrate is an IC package.

12. The IC package of claim 1 , wherein the first-level interconnects include solder.

13. The IC package of claim 1 , wherein the first-level interconnects do not include solder.

14. The IC package of claim 1 , wherein the solder resist includes a polymer.

15. The IC package of claim 1 , further comprising:
an underfill material between the die and the redistribution structure.

16. The IC package of claim 15 , further comprising:
a mold material on the die such that the die is between at least a part of the mold material and the underfill material.

17. The IC package of claim 16 , wherein the underfill material and the mold material are a same material.

18. The IC package of claim 17 , wherein the underfill material has a filler cut greater than or equal to 15 μm.

19. The IC package of claim 15 , wherein the underfill material has a filler cut greater than or equal to 15 μm.

20. The computing assembly of claim 7 , wherein the second-level interconnects are ball grid array (BGA) interconnects.

21. The computing assembly of claim 7 , wherein the second-level interconnects are land grid array (LGA) interconnects.

22. The computing assembly of claim 7 , wherein the first-level interconnects do not include solder.

23. The computing assembly of claim 7 , wherein the second-level interconnects include solder at least partially in the openings in the solder resist.

24. The IC package of claim 1 , wherein a thickness of the solder resist layer is greater than a thickness of a redistribution layer at bottoms of the openings.

25. The computing assembly of claim 7 , wherein a thickness of the solder resist layer is greater than a thickness of the redistribution layer.

Assignees

• Ganesan Sanka
• Meyer Thorsten
• Ofner Gerald
• Intel Ip Corp

Inventors

• Ganesan Sanka
• Meyer Thorsten
• Ofner Gerald

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title