Transistor structure with n/p boundary buffer

Patent metadata

Field	Value
Publication number	US-10903124-B2
Application number	US-201916399864-A
Country	US
Kind code	B2
Filing date	Apr 30, 2019
Priority date	Apr 30, 2019
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.

First claim

What is claimed is:

1. A method of removing gate metal from a region of field-effect transistors, comprising:
obtaining a monolithic structure including first and second regions, the first region including a first field-effect transistor structure, the second region including a second field-effect transistor structure, a trench between the first field-effect transistor structure and the second field-effect transistor structure, the trench extending over a boundary between the first region and the second region, a layer of gate dielectric material extending between the first and second field-effect transistor structures and across the trench, and a layer of gate metal extending over channel regions of the first and second field-effect transistor structures and over the layer of gate dielectric material;
depositing a dielectric spacer layer over the monolithic structure, the dielectric spacer layer extending over the first and second field-effect transistor structures and having a horizontal segment extending across a bottom surface of the trench;
removing at least a portion of the horizontal segment of the dielectric spacer layer, thereby exposing a portion of the layer of gate metal between the first field-effect transistor structure and the second field-effect transistor structure;
conducting a first etch of the layer of gate metal, thereby causing removal of the exposed portion of the gate metal layer between the first field-effect transistor structure and the second field-effect transistor structure;
forming a patterned buffer layer over the first region of the monolithic structure;
removing the dielectric spacer layer from the second region of the monolithic structure; and
subjecting the monolithic structure to a wet second etch, thereby removing the layer of gate metal from the second field-effect transistor structure while the gate metal extending around the first field-effect transistor structure remains intact.

2. The method of claim 1 , wherein the first field-effect transistor structure and the second field-effect transistor structure are nanosheet field-effect transistor structures including nanosheet channel regions, further including:
conducting the first etch of the layer of gate metal causes partial undercutting of the layer of gate metal beneath the dielectric spacer layer, though not directly beneath the nanosheet channel regions, in both the first region and the second region of the monolithic structure.

3. The method of claim 2 , further including removing a portion of the layer of gate dielectric material over the boundary between the first region and the second region.

4. The method of claim 1 , wherein the first field-effect transistor structure and the second field-effect transistor structure comprise first and second nanosheet field-effect transistor structures including nanosheet channel regions, further including:
forming a protective layer on a top surface of the dielectric spacer layer, the protective layer including a first portion over the first nanosheet transistor structure and a second portion over the second nanosheet transistor structure.

5. The method of claim 4 , wherein forming the protective layer on the top surface of the dielectric spacer layer includes subjecting the dielectric spacer layer to angled ion implantation such that the horizontal segment of the dielectric spacer layer remains essentially unprotected by the protective layer.

6. The method of claim 4 , wherein forming the protective layer on the top surface of the dielectric spacer layer includes subjecting the dielectric spacer layer to angled physical vapor deposition of a hard mask material such that the horizontal segment of the dielectric spacer layer remains essentially unprotected by the protective layer.

7. The method of claim 4 , wherein forming the protective layer on the top surface of the dielectric spacer layer includes:
forming a protective coating over the monolithic structure;
removing portions of the protective coating, thereby exposing the top surface of the dielectric spacer layer, and
forming the protective layer on the top surface of the exposed dielectric spacer layer.

8. The method of claim 7 , wherein forming the protective layer includes spin coating a polymer brush on the top surface of the exposed dielectric spacer layer and baking the polymer brush.

9. The method of claim 8 , wherein the polymer brush comprises poly-hydroxy styrene.

10. The method of claim 9 , wherein the protective coating is an organic planarization layer, further including removing the organic planarization layer following spin coating the polymer brush on the top surface of the exposed dielectric spacer layer and baking the polymer brush.

11. The method of claim 1 , further including removing a portion of the layer of gate dielectric material over the boundary between the first region and the second region and removing the dielectric spacer layer from the first region of the monolithic structure prior to forming the patterned buffer layer over the first region of the monolithic structure.

12. The method of claim 11 , wherein the patterned buffer layer is formed over the dielectric spacer layer.

13. The method of claim 11 , wherein the first field-effect transistor structure and the second field-effect transistor structure are nanosheet field-effect transistor structures including nanosheet channel regions, further wherein conducting the first etch of the layer of gate metal causes formation of a pair of cavities extending laterally from the trench and beneath the dielectric spacer layer in both the first region and the second region of the monolithic structure, and further wherein the patterned buffer layer covers the cavity in the first region of the monolithic structure.

Assignees

• IBM

Inventors

• Lallement Romain
• Seshadri Indira
• Bao Ruqiang

Classifications

• H10P14/3451

  Structure · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title