Memory access based I/O operations

Patent metadata

Field	Value
Publication number	US-10901910-B2
Application number	US-201815946079-A
Country	US
Kind code	B2
Filing date	Apr 5, 2018
Priority date	Apr 5, 2018
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

The invention relates to a method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device. An operating system provides a trigger address range in a virtual address space assigned to the computer program. A page fault is caused by accessing the trigger address by the computer program. A page fault handler handling the page fault acquires information for identifying the data to be transferred using the trigger address. The acquired information is provided to the input/output device and the identified data is transferred between the memory and the input/output device.

First claim

What is claimed is:

1. A method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device, wherein the memory is managed by an operating system which maps the memory with a virtual address space assigned to the computer program, wherein the method comprises:
providing by the operating system an additional trigger address range in the virtual address space, the trigger address range comprising at least one trigger address labeled invalid for causing a page fault when being accessed by the computer program and triggering the data transfer;
generating a page fault by accessing the trigger address by the computer program, the page fault comprising interrupting the execution of the computer program;
in response to the page fault, initiating an execution of a page fault handler of the operating system assigned for handling page faults caused by accessing virtual addresses comprised by the trigger address range;
acquiring information for identifying the data to be transferred by the page fault handler using the trigger address and providing the acquired information to the input/output device; and
in response to the providing of the acquired information, transferring the identified data from the memory to the input/output device.

2. The method of claim 1 , wherein the trigger address encodes metadata identifying the data to be transferred.

3. The method of claim 1 , wherein the trigger address identifies metadata stored in the memory, the stored metadata identifying the data to be transferred.

4. The method of claim 3 , wherein the acquired information for identifying the data to be transferred comprises a pointer to the metadata stored in the memory, wherein the input/output device uses the pointer to retrieve the metadata from the memory.

5. The method of claim 3 , wherein the metadata comprises one or more of an identifier of the transfer operation to be executed, an identifier of the origin location of the data to be transferred, an identifier of the target location of the data to be transferred, and an identifier of the size of the data to be transferred.

6. The method of claim 1 , wherein the computer program is a process virtual machine in a platform-independent runtime environment executing an application.

7. The method of claim 6 , wherein the process virtual machine is a Java virtual machine in a Java runtime environment, wherein the application is a Java application, and wherein the memory is an off-heap memory.

8. The method of claim 1 , wherein the data to be transferred is stored in the memory by the computer program.

9. The method of claim 1 , wherein the accessing of the trigger address comprises using a data store instruction, and wherein the method further comprises initiating a skipping of the execution of the store instruction by the page fault handler when continuing the execution of the computer program by the processor.

10. The method of claim 1 , wherein the memory is accessible by firmware of the input/output device and wherein the transferring of the identified data comprises retrieving the identified data from the memory by the firmware which provides the retrieved data to hardware of the input/output device.

11. The method of claim 1 , wherein the memory is accessible by the hardware of the input/output device and wherein the transferring of the identified data comprises retrieving the identified data from the memory by the hardware.

12. The method of claim 11 , wherein a translation of a virtual address of the identified data to be transferred to a physical address is registered and provided to the hardware of the input/output device by the page fault handler in order to enable the hardware to address the respective data.

13. The method of claim 11 , wherein the retrieving of the identified data by the hardware of the input/output device is completed asynchronously, while the execution of the computer program by the processor is continued.

14. The method of claim 1 , wherein the data to be transferred is pinned in the memory in response to the initiating of the execution of the page fault handler, wherein the pinning prevents the data to be transferred from being swapped out of the memory for being stored in an additional computer storage.

15. The method of claim 1 , wherein a pinned transfer section comprised by the memory is provided for storing the data to be transferred, wherein the pinning of the transfer section prevents data comprised by the transfer section from being swapped out of the memory for being stored in the additional computer storage.

16. The method of claim 1 , wherein the data is further transferred from the input/output device to the memory.

17. The method of claim 16 , wherein the accessing of the trigger address comprises using a data load instruction, and wherein the method further comprises initiating a repetition of the execution of the load instruction by the page fault handler when continuing the execution of the computer program by the processor.

18. A computer system comprising a memory, a processor for executing a computer program and an input/output device, wherein the computer system is configured for transferring data between the computer program and the input/output device using a memory accessible by the computer program and the input/output device, wherein the memory is managed by an operating system which maps the memory with a virtual address space assigned to the computer program, wherein the transferring comprises:
providing by the operating system an additional trigger address range in the virtual address space, the trigger address range comprising at least one trigger address labeled invalid for causing a page fault when being accessed by the computer program and triggering the data transfer;
generating a page fault by accessing the trigger address by the computer program, the page fault comprising interrupting the execution of the computer program;
in response to the page fault, initiating an execution of a page fault handler of the operating system assigned for handling page faults caused by accessing virtual addresses comprised by the trigger address range;
acquiring information for identifying the data to be transferred by the page fault handler using the trigger address and providing the acquired information to the input/output device; and
in response to the providing of the acquired information, transferring the identified data from the memory to the input/output device.

19. A computer program product comprising a computer-readable storage medium having machine executable program instructions embodied therewith, the machine executable program instructions being configured to implement a method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device, wherein the memory is managed by an operating system which maps the memory with a virtual address space assigned to the computer program, wherein the method comprises:
providing by the operating system an additional trigger address range in the virtual address space, the trigger address range comprising at least one trigger address labeled invalid for causing a page fault when being accessed by the computer program and triggering the data transfer;
generating a page fault by accessing the trigger address by the computer program, the page fault comprising interrupting the execution of the c

Assignees

• IBM

Inventors

• Raisch Christoph
• Otte Carsten
• Brachmann Matthias
• Kraemer Marco

Classifications

• G06F12/126 Primary

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F2212/657

  Virtual address space management · CPC title