Memory device specific self refresh entry and exit

Patent metadata

Field	Value
Publication number	US-2016350002-A1
Application number	US-201514998058-A
Country	US
Kind code	A1
Filing date	Dec 26, 2015
Priority date	May 29, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.

First claim

What is claimed is:

1 . A buffer circuit in a memory subsystem, comprising:
an interface to a control bus, the control bus to be coupled to multiple memory devices; an interface to a data bus, the data bus to be coupled to the multiple memory devices; control logic to send a device specific self-refresh exit command over the control bus when the multiple memory devices are in self-refresh, the command including a unique memory device identifier to cause only an identified memory device to exit self-refresh while the other memory devices remain in self-refresh, and the control logic to perform data access over the data bus for the memory device caused to exit self-refresh.

2 . The buffer circuit of claim 1 , wherein the control logic is further to select a subset of the multiple memory devices, and send device specific self-refresh exit commands to each of the selected memory devices of the subset.

3 . The buffer circuit of claim 1 , wherein the self-refresh exit command includes a CKE (clock enable) signal.

4 . The buffer circuit of claim 1 , wherein the control logic is further to select the memory devices in turn to cause serial memory access to all of the memory devices.

5 . The buffer circuit of claim 1 , wherein the buffer circuit comprises a registered clock driver (RCD) of an NVDIMM (nonvolatile dual inline memory module), wherein the control logic is further to transfer self-refresh commands to all memory devices to place the memory devices in self-refresh as part of a backup transfer process to transfer memory contents to a persistent storage upon detection of a power failure.

6 . The buffer circuit of claim 5 , wherein the interface to the data bus comprises an interface to an alternate data bus parallel to a primary data bus used by the memory devices in active operation, and wherein the control logic is to cause the memory devices to transfer memory contents via the alternate data bus as part of the backup transfer process.

7 . The buffer circuit of claim 1 , wherein the buffer circuit comprises a backup controller of a registered DIMM (RDIMM).

8 . The buffer circuit of claim 1 , wherein after the performance of data access with a selected memory device, the control logic further to send a device specific self-refresh command including a self-refresh enter command and the unique memory device identifier over the control bus to cause the selected memory device to re-enter self-refresh.

9 . The buffer circuit of claim 1 , wherein the memory devices share the control bus as part of a memory rank that shares a command/address bus.

10 . A nonvolatile dual inline memory module (NVDIMM), comprising:
a first data bus; a second data bus; multiple volatile memory devices coupled to a common control line shared by the memory devices, the memory devices further to couple to a nonvolatile storage via the second data bus; and control logic coupled to the memory devices via the first data bus and via the common control line, the control logic including control logic to send a device specific self-refresh exit command over the control line when the multiple memory devices are in self-refresh, the command including a unique memory device identifier to cause only an identified memory device to exit self-refresh while the other memory devices remain in self-refresh, and the control logic to cause the identified memory device to transfer memory contents via the second memory bus while the other memory devices remain in self-refresh.

11 . The NVDIMM of claim 10 , wherein the memory devices include dual data rate version 4 synchronous dynamic random access memory devices (DDR4-SDRAMs).

12 . The NVDIMM of claim 10 , wherein the nonvolatile storage comprises a storage device disposed on the NVDIMM.

13 . The NVDIMM of claim 10 , wherein the second data bus is to couple to a nonvolatile storage device located external to the NVDIMM.

14 . The NVDIMM of claim 10 , wherein the control logic is further to selectively cause one memory device at a time to exit self-refresh, transfer memory contents to the nonvolatile storage, and then return to self-refresh, repeating for all memory devices in turn in response to detection of a power failure.

15 . The NVDIMM of claim 10 , wherein the memory devices are part of a same memory rank, and the control line comprises a command/address bus for the memory rank.

16 . The NVDIMM of claim 10 , wherein the control logic comprises a registered clock driver (RCD).

17 . A method memory management, comprising:
selecting for data access one of multiple memory devices that share a control bus, wherein the memory devices are in self-refresh; sending a device specific self-refresh exit command including a self-refresh exit command and a unique memory device identifier over the shared control bus to cause only the selected memory device to exit self-refresh while the others remain in self-refresh; and performing data access over a shared data bus for the memory device not in self-refresh.

18 . The method of claim 17 , wherein selecting comprises selecting a subset of memory devices, and sending the device specific self-refresh exit command comprises sending device specific commands to each memory device of the selected subset.

19 . The method of claim 17 , wherein selecting comprises selecting each memory device individually to cause serial memory access to the memory devices.

20 . The method of claim 17 , wherein the memory devices comprise memory devices of a registered DIMM (RDIMM).

21 . The method of claim 17 , further comprising:
after performing the data access with the selected memory device, sending a device specific self-refresh command including a self-refresh command and the unique memory device identifier over the shared control bus to cause the selected memory device to re-enter self-refresh.

Assignees

• Intel Corp

Inventors

• Vergis George
• Bains Kuljit S
• Mccall James A
• Nachimuthu Murugasamy K
• Kumar Mohan J

Classifications

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0605 Primary

  by facilitating the interaction with a user or administrator · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title