Liquid crystal display device

Patent metadata

Field	Value
Publication number	US-10901283-B2
Application number	US-201916519110-A
Country	US
Kind code	B2
Filing date	Jul 23, 2019
Priority date	Nov 14, 2008
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first transistor, a second transistor, a third transistor, and a fourth transistor
wherein one of a source and a drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the first transistor is directly connected to a gate line,
wherein one of a source and a drain of the second transistor is directly connected to a second wiring,
wherein the other of the source and the drain of the second transistor is directly connected to the gate line,
wherein one of a source and a drain of the fourth is directly connected to the second wiring,
wherein the other of the source and the drain of the fourth transistor is directly connected to the gate line,
wherein by turning on the first transistor, a signal that turns on the third transistor is supplied to the gate line,
wherein by turning on the second transistor, a signal that turns off the third transistor is supplied to the gate line,
wherein a gate of the third transistor is directly connected to the gate line,
wherein by turning on the fourth transistor, a signal that turns off the third transistor is supplied to the gate line, and
wherein a signal whose potential is changed between a first potential and a second potential is supplied to the second wiring.

2. A semiconductor device, comprising:
a gate driver, a first pixel, and a second pixel,
wherein the gate driver comprises a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein the first pixel comprises a fifth transistor,
wherein the second pixel comprises a sixth transistor,
wherein one of a source and a drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the first transistor is directly connected to a first gate line,
wherein one of a source and a drain of the second transistor is directly connected to a second wiring,
wherein the other of the source and the drain of the second transistor is directly connected to the first gate line,
wherein by turning on the first transistor, a signal that turns on the fifth transistor is supplied to the first gate line,
wherein by turning on the second transistor, a signal that turns off the fifth transistor is supplied to the first gate line,
wherein one of a source and a drain of the third transistor is directly connected to a third wiring,
wherein the other of the source and the drain of the third transistor is directly connected to a second gate line,
wherein one of a source and a drain of the fourth is directly connected to the second wiring,
wherein the other of the source and the drain of the fourth transistor is directly connected to the second gate line,
wherein by turning on the third transistor, a signal that turns on the sixth transistor is supplied to the second gate line,
wherein by turning on the fourth transistor, a signal that turns off the sixth transistor is supplied to the second gate line,
wherein a gate of the fifth transistor is directly connected to the first gate line,
wherein a gate of the sixth transistor is directly connected to the second gate line,
wherein a clock signal is supplied to the first wiring, and
wherein a signal whose potential is changed between a first potential and a second potential is supplied to the second wiring.

3. A semiconductor device, comprising:
a first stage;
a second stage that comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; and
a third stage,
wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, a gate of the fourth transistor, one of a source and a drain of the seventh transistor, a gate of the eighth transistor, a gate of the ninth transistor, and a gate of the eleventh transistor are directly connected to each other,
wherein a gate of the first transistor, and a gate of the sixth transistor are directly connected to the first stage,
wherein a gate of the second transistor is directly connected to the third stage
wherein one of a source and a drain of the third transistor, and a gate of the third transistor are directly connected to each other,
wherein the other of the source and the drain of the third transistor, one of a source and a drain of the fourth transistor, and a gate of the fifth transistor are directly connected to each other,
wherein one of a source and a drain of the fifth transistor, one of a source and a drain of the sixth transistor, a gate of the seventh transistor, one of a source and a drain of the eighth transistor, a gate of the tenth transistor, and a gate of the twelfth transistor are directly connected to each other,
wherein one of a source and a drain of the ninth transistor, and one of a source and a drain of the tenth transistor are directly connected to the first stage and the third stage,
wherein one of a source and a drain of the eleventh transistor, and one of a source and a drain of the twelfth transistor are directly connected to a pixel,
wherein the other of the source and the drain of the ninth transistor, and the other of the source and the drain of the eleventh transistor are directly connected to a first wiring,
wherein the other of the source and the drain of the second transistor is directly connected to a second wiring, and
wherein the other of the source and the drain of the twelfth transistor is directly connected to a third wiring.

Assignees

• Semiconductor Energy Lab

Inventors

• Kimura Hajime

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title