Liquid crystal display device

Patent metadata

Field	Value
Publication number	US-10416517-B2
Application number	US-201715668737-A
Country	US
Kind code	B2
Filing date	Aug 4, 2017
Priority date	Nov 14, 2008
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

First claim

What is claimed is:

1. A semiconductor device comprising:
a shift register circuit;
wherein the shift register circuit comprises first to eighth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
wherein the gate of the first transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the first transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the gate of the first transistor is electrically connected to a gate of the seventh transistor,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein the gate of the second transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the gate of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the fourth wiring,
wherein a gate of the eighth transistor is electrically connected to the fourth wiring.

2. A semiconductor device comprising:
a shift register circuit;
wherein the shift register circuit comprises a first stage and a second stage,
wherein the first stage comprises first to eighth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
wherein the gate of the first transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the first transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the gate of the first transistor is electrically connected to a gate of the seventh transistor,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein the gate of the second transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the gate of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the fourth wiring,
wherein a gate of the eighth transistor is electrically connected to the fourth wiring,
wherein the second stage comprises a ninth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the ninth transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a pixel.

3. A semiconductor device comprising:
a shift register circuit;
wherein the shift register circuit comprises first to twelfth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a gate of the first transistor is electrically connected to a gate of the third transistor,
wherein the gate of the first transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the first transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the gate of the first transistor is electrically connected to a gate of the seventh transistor,
wherein the gate of the first transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the gate of the second transistor is electrically connected to a gate of the fifth transistor,
wherein the gate of the second transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the gate of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the fourth wiring,
wherein a gate of the eighth transistor is electrically connected to the fourth wiring,
wherein a gate of the ninth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the eleventh transisto

Assignees

• Semiconductor Energy Lab

Inventors

• Kimura Hajime

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0254

  Control of polarity reversal in general, other than for liquid crystal displays · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title