Pulse output circuit, shift register, and display device

Patent metadata

Field	Value
Publication number	US-9064753-B2
Application number	US-201414318809-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Oct 17, 2006
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.

First claim

What is claimed is:

1. A pulse output circuit comprising:
first, second, third, fourth, and fifth transistors;
first, second, third and fourth input terminals; and
an output terminal;
wherein a first electrode of the first transistor is electrically connected to the first input terminal, and a second electrode of the first transistor is electrically connected to the output terminal,
wherein a first electrode of the second transistor is configured to be supplied with a first potential, and a second electrode of the second transistor is electrically connected to the output terminal,
wherein a first electrode of the third transistor is configured to be supplied with the first potential, a second electrode of the third transistor is electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor is electrically connected to the fourth input terminal,
wherein a second electrode of the fourth transistor is electrically connected to a second electrode of the fifth transistor, and a gate electrode of the fourth transistor is electrically connected to the second input terminal, and
wherein a first electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fifth transistor is electrically connected to the third input terminal.

2. The pulse output circuit according to claim 1 , wherein each of the first, second, third, fourth, and fifth transistors comprises silicon.

3. The pulse output circuit according to claim 1 , wherein each of the first, second, third, fourth, and fifth transistors comprises amorphous silicon.

4. The pulse output circuit according to claim 1 , wherein a channel width of the third transistor is larger than a channel width of the fourth transistor and a channel width of the fifth transistor.

5. The pulse output circuit according to claim 1 , wherein the gate electrode of the second transistor is configured to be supplied with a voltage through the fourth transistor and the fifth transistor.

6. The pulse output circuit according to claim 1 , wherein a first electrode of the fourth transistor is electrically connected to a fifth power supply line.

7. A display device comprising:
a pixel portion over a substrate; and
a driver circuit for driving the pixel portion, the driver circuit comprising an pulse output circuit which comprises:
first, second, third, fourth, and fifth transistors;
first, second, third and fourth input terminals; and
an output terminal;

wherein a first electrode of the first transistor is electrically connected to the first input terminal, and a second electrode of the first transistor is electrically connected to the output terminal,
wherein a first electrode of the second transistor is configured to be supplied with a first potential, and a second electrode of the second transistor is electrically connected to the output terminal,
wherein a first electrode of the third transistor is configured to be supplied with the first potential, a second electrode of the third transistor is electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor is electrically connected to the fourth input terminal,
wherein a second electrode of the fourth transistor is electrically connected to a second electrode of the fifth transistor, and a gate electrode of the fourth transistor is electrically connected to the second input terminal, and
wherein a first electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fifth transistor is electrically connected to the third input terminal.

8. The display device according to claim 7 , wherein each of the first, second, third, fourth, and fifth transistors comprises silicon.

9. The display device according to claim 7 , wherein each of the first, second, third, fourth, and fifth transistors comprises amorphous silicon.

10. The display device according to claim 7 , wherein a channel width of the third transistor is larger than a channel width of the fourth transistor and a channel width of the fifth transistor.

11. The display device according to claim 7 , wherein the gate electrode of the second transistor is configured to be supplied with a voltage through the fourth transistor and the fifth transistor.

12. The display device according to claim 7 , wherein a first electrode of the fourth transistor is electrically connected to a fifth power supply line.

Assignees

• Semiconductor Energy Lab

Inventors

• Miyake Hiroyuki

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title