Formation of wrap-around-contact to reduce contact resistivity

Patent metadata

Field	Value
Publication number	US-10896965-B2
Application number	US-201916692809-A
Country	US
Kind code	B2
Filing date	Nov 22, 2019
Priority date	Jul 3, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

First claim

What is claimed is:

1. A field effect transistor; comprising:
a gate structure on a substrate;
a source/drain on each of opposite sides of the gate structure and on the substrate;
a source/drain contact on each of the source/drains, wherein each of the source/drain contacts wraps around the sides of one source/drain;
an interlayer dielectric (ILD) layer on opposite sides of each of the source/drain contacts; and
a dielectric protective liner between the ILD layer and the source/drain contact, wherein a portion of each source/drain contact between an underlying source/drain and the dielectric protective liner has an outer shape that matches the outer shape on both sides of the underlying source/drain, and the dielectric protective liner is in contact with the substrate.

2. The field effect transistor of claim 1 , wherein each of the source/drain contacts is formed of a material selected from the group consisting of titanium (Ti), cobalt (Co), and nickel (Ni).

3. The field effect transistor of claim 1 , wherein a portion of the source/drain contact in physical contact with the source/drain has a thickness in a range of about 2 nm to about 4 nm.

4. The field effect transistor of claim 1 , wherein the source/drain contacts are in direct contact with a portion of the substrate on opposite sides of the source/drain.

5. The field effect transistor of claim 1 , further comprising a stack of channel layers between the source/drains, wherein each of the source/drains is in physical and electrical contact with the stack of channel layers.

6. The field effect transistor of claim 5 , further comprising a protective liner on a portion of a gate sidewall spacer of the gate structure.

7. The field effect transistor of claim 6 , wherein each of the source/drain contacts is in direct contact with a portion of the gate sidewall spacer.

8. The field effect transistor of claim 7 , further comprising an inner spacer on each of opposite sides of each channel layer.

9. A field effect transistor; comprising:
a gate structure on a substrate, wherein the gate structure includes a gate sidewall spacer;
a source/drain on opposite sides of the gate structure and on the substrate;
a source/drain contact on opposite sides of each of the source/drains, wherein each of the source/drain contacts wraps around the sides of source/drain and is in contact with the substrate on both sides of the source/drain;
an interlayer dielectric (ILD) layer on each of the source/drain contacts; and
a dielectric protective liner between the ILD layer and the source/drain contact, wherein a portion of each source/drain contact has a thickness in a range of about 2 nm to about 5 nm on both sides of the source/drain that is between an underlying source/drain and the dielectric protective liner, and wherein the dielectric protective liner is on the substrate adjacent to the source/drain contact.

10. The field effect transistor of claim 9 , wherein each of the source/drain contacts is in direct contact with a portion of the gate sidewall spacer.

11. The field effect transistor of claim 10 , wherein the source/drain contacts are in direct contact with a portion of the substrate.

12. The field effect transistor of claim 11 , wherein the source/drains are boron doped silicon germanium (SiGe).

13. The field effect transistor of claim 11 , wherein the boron doped silicon-germanium source/drain have a germanium (Ge) concentration gradient from the outer surface inwards.

14. A field effect transistor; comprising:
a gate structure on a substrate, wherein the gate structure includes a gate sidewall spacer;
a source/drain on opposite sides of the gate structure and on the substrate;
a source/drain contact on opposite sides of each of the source/drains, wherein each of the source/drain contacts wraps around the sides of source/drain and is in contact with the substrate on both sides of the source/drain;
an interlayer dielectric (ILD) layer on opposite sides of each of the source/drain contacts;
a dielectric protective liner between the ILD layer and the source/drain contact, wherein a portion of each source/drain contact between an underlying source/drain and the dielectric protective liner has an outer shape that matches the outer shape on both sides of the underlying source/drain, and wherein the dielectric protective liner is in contact with the substrate adjacent to the source/drain contact; and
a stack of channel layers between the source/drains, wherein each of the source/drains is in physical and electrical contact with the stack of channel layers.

15. The field effect transistor of claim 14 , wherein the protective liner is a dielectric material selected from the group consisting of silicon nitride (SiN) and silicon carbonitride (SiCN).

16. The field effect transistor of claim 15 , wherein each of the source/drain contacts is formed of a material selected from the group consisting of titanium (Ti), cobalt (Co), and nickel (Ni).

17. The field effect transistor of claim 16 , wherein a portion of the source/drain contact in physical contact with the source/drain has a thickness in a range of about 2 nm to about 4 nm.

Assignees

• IBM

Inventors

• Carr Adra
• Zhang Jingyun
• Lee Choonghyun
• Ando Takashi
• Hashemi Pouya

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title