Bus synchronization system that aggregates status

Patent metadata

Field	Value
Publication number	US-10896106-B2
Application number	US-201815976407-A
Country	US
Kind code	B2
Filing date	May 10, 2018
Priority date	May 10, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

An example test system includes instruments for controlling testing. Each instrument may be controlled by a processing unit. Each processing unit may be configured to operate on portions of a test program relevant to an instrument that the processing unit controls. A synchronization mechanism operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller.

First claim

What is claimed is:

1. A system comprising:
a computer bus;
a host computer to execute test flows; and
instrument modules, an instrument module comprising:
resources; and
a processing device;

wherein resources operated on by a test flow define a domain;
wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
wherein the processing device is configured to resume executing commands based on the information;
wherein the instrument module comprises an endpoint device to provide status to the computer bus;
wherein the endpoint device comprises a contributing endpoint device; and
wherein the contributing endpoint device is configured to receive the information from the computer bus and to generate a signal based on the information to trigger operation of one or more of the resources.

2. A system comprising:
a computer bus;
a host computer to execute test flows; and
instrument modules, an instrument module comprising:
resources; and
a processing device;

wherein resources operated on by a test flow define a domain;
wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
wherein the processing device is configured to resume executing commands based on the information;
wherein the instrument module comprises an endpoint device; and
wherein the endpoint device comprises a non-contributing endpoint device to receive the information from the computer bus and to generate a signal based on the information to trigger operation of one or more of the resources.

3. The system of claim 1 or 2 , wherein the host computer is programmed to output the commands to the instrument modules via a communication bus that is different from the computer bus.

4. The system of claim 1 or 2 , wherein aggregating the status and distributing the information are performed independent of the host computer.

5. The system of claim 1 or 2 , wherein at least some of the commands instruct resources in the domain to perform operations.

6. The system of claim 1 or 2 , wherein the signal is to trigger a resource to perform an action for which the resource has been previously armed.

7. The system of claim 1 , wherein an offset may be added to the signal to control signal timing relative to receipt of the information.

8. The system of claim 1 or 2 , wherein the endpoint device comprises a transmitter to implement output to the computer bus, and a receiver to implement receiving from the computer bus.

9. The system of claim 1 or 2 , further comprising a processor to perform a test;
wherein the status comprises a pass or fail status of the test performed by the processor.

10. The system of claim 1 or 2 , wherein the computer bus comprises at least one of a wired-OR bus; point-to-point connections and logic gates; non-contact, wireless or optical signaling; or a combination of one or more of: a wired-OR bus; point-to-point connections and logic gates; non-contact, and wireless or optical signaling.

11. The system of claim 1 or 2 , wherein the information is received over the computer bus.

12. The system of claim 1 or 2 , wherein the information is received over a communication bus that is different than the computer bus.

13. The system of claim 1 or 2 , wherein the sync command in the test flow immediately precedes, in the test flow, a command requiring action or measurement vis-à-vis a device under test by the test flow.

14. The system of claim 1 or 2 , wherein at least part of the test flow is controllable not to be synchronized.

15. The system of claim 1 or 2 , wherein the information is distributed after all instrument modules in the domain have encountered a sync command.

16. A system comprising:
a computer bus;
a host computer to execute test flows; and
instrument modules, an instrument module comprising:
resources; and
a processing device;

wherein resources operated on by a test flow define a domain;
wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
wherein the processing device is configured to resume executing commands based on the information;
wherein the host computer is programmed to execute a test program that includes multiple, separate instruction flows, the multiple, separate instruction flows including the test flow;
wherein the instrument module comprises an endpoint device; and
wherein the endpoint device is configured to subscribe to one or more of the multiple, separate instruction flows.

17. A system comprising:
a computer bus;
a host computer to execute test flows; and
instrument modules, an instrument module comprising:
resources; and
a processing device;

wherein resources operated on by a test flow define a domain;
wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
wherein the processing device is configured to resume executing commands based on the information; and
wherein the status comprises bits that are encoded in time-division-multiple-access fashion onto the computer bus using a periodic frame comprised of multiple bits.

18. The system of claim 17 , wherein the periodic frame is characterized by one or more of headers, trailers, cyclic redundancy checks, or 8b/10b encoding.

19. A system comprising:
a computer bus;
a host computer to execute test flows; and
instrument modules, an instrument module comprising:
resources; and
a processing device;

wherein resources operated on by a test flow define a domain;
wherein the host computer is configured to output commands including a sync command in the test flow to the instrument modules, the sync command for causing the instrument module to provide a status to the computer bus and to pause the processing device;
wherein statuses from the instrument modules in the domain are aggregated on the computer bus, and wherein information is distributed to the instrument modules based on the statuses aggregated;
wherein the processing device is configured to resume executing commands based on the information; and
wherein at least some bits of the information rep

Assignees

• Teradyne Inc

Inventors

• Panis Michael C
• Benagh Jeffrey S
• Pye Richard

Classifications

• G06F11/2236

  to test CPU or processors · CPC title

• G06F13/423

  with synchronous protocol · CPC title

• G01R31/318314

  Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261) · CPC title

• G01R31/318307

  computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging · CPC title

• G01R31/31726 Primary

  Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals · CPC title