Test system supporting simplified configuration for controlling test block concurrency

Patent metadata

Field	Value
Publication number	US-10048304-B2
Application number	US-201113281148-A
Country	US
Kind code	B2
Filing date	Oct 25, 2011
Priority date	Oct 25, 2011
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows, the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

First claim

What is claimed is:

1. A method of operating a test system to test a device that has a plurality of cores, each core having a plurality of pins, and the test system having multiple tester-sites, each tester-site having hardware resources, and a signal delivery interface that is configurable to connect the hardware resources to the pins, the method comprising:
configuring the test system by connecting the hardware resources to the plurality of pins of the plurality of cores, wherein the hardware resources are connected through the signal delivery interface configured in accordance with a mapping, wherein the mapping comprises a plurality of flow domains, each flow domain being associated with at least one core of the plurality of cores and wherein the mapping specifies connections between each of a plurality of tester-sites and an associated core of the plurality of cores such that the hardware resources of each tester site are connected to access the pins of the associated core and the hardware resources connected to pins of cores in each of the plurality of flow domains are operable independently of the hardware resources connected to pins of cores in the others of the plurality of flow domains; and
executing a test flow with a plurality of test blocks, each test block testing a core of the plurality of cores by controlling hardware resources in the associated tester site to generate or measure one or more types of signals at the pins of the core being tested, some of the test blocks being executed concurrently so as to provide a first sub-flow and a second sub-flow,
wherein:
the cores tested by test blocks in each sub-flow are associated with a flow domain of the plurality of flow domains;
the executing comprises independently taking action in each of the first sub-flow and the second sub-flow; and
independently taking action comprises executing a test block of the plurality of test blocks based on alarm detection in the second sub-flow and independent of alarm detection in the first sub-flow.

2. The method of claim 1 , wherein:
executing the test flow with the plurality of test blocks with some of the test blocks being executed concurrently comprises:
at a first time, executing a first portion of the plurality of test blocks concurrently; and
at a second time, executing a second portion of the plurality of test blocks sequentially such that, during sequential execution of the second portion of the test blocks, a single test block is executed at a time.

3. The method of claim 1 , wherein:
the plurality of cores comprises cores of a plurality of types; and
the method further comprises partitioning the tester sites into groups, each of the groups being mapped to a type of the plurality of types of cores.

4. The method of claim 1 , wherein:
the plurality of tester sites include flow domain specific resources, global resources and sequential resources.

5. The method of claim 1 , further comprising:
configuring the test system at a first time during execution of a test flow to use a first resource in a first flow domain; and
configuring the test system at a second time during execution of the test flow to use the first resource in a second flow domain.

6. A method of operating a test system of the type having hardware resources that can be associated with at least one tester site of a plurality of tester sites, each tester site having a site identifier such that hardware resources of the test system associated with a tester site process a command directed to the site, the method comprising:
configuring the test system to test at least one semiconductor component comprising a plurality of pins and a plurality of cores, each core comprising a sub-set of the plurality of pins, the configuring comprising, for each of the plurality of cores, associating a tester site of the plurality of tester sites with the core such that hardware resources associated with the tester site access corresponding pins of the associated core during a test; and
executing a plurality of test blocks in accordance with a test flow, each of the test blocks being configured to test a respective at least one associated core, a portion of the plurality of test blocks being executed concurrently in a plurality of sub-flows, each of the plurality of test blocks controlling operation of hardware resources in a tester site associated with the respective at least one associated core to generate or measure one or more types of signals at the pins of the at least one associated core,
wherein at least one of the plurality of test blocks is executed to control operation of an instrument to generate or measure a voltage or current at a digital pin of the semiconductor component, and
wherein the test system comprises hardware components to perform localized alarming associated with at least one sub-flow.

7. The method of claim 6 , further comprising:
receiving user input defining flow domains grouping pins, each flow domain including the pins of a core accessible by a tester site;
allocating tester sites to the flow domains.

8. The method of claim 6 , further comprising:
generating information for configuring the test system by:
receiving, at a computing device, user input identifying groups of the plurality of pins, each group indicating pins accessed during test of a core of the plurality of cores; and
with the computing device, determining an allocation of tester sites of the plurality of tester sites to the identified groups.

9. The method of claim 8 , wherein:
there are no overlaps between the tester sites associated with the identified groups.

10. The method of claim 8 , wherein:
hardware resources associated with different ones of the identified groups are isolated from each other.

11. The method of claim 8 , wherein flow domain specific processing is performed.

12. The method of claim 11 , wherein the flow domain specific processing comprises a site loop.

13. The method of claim 8 , wherein:
each of the identified groups of pins is accessed within a sub-flow in which an associated test block is executed; and
executing the plurality of test blocks comprises, for each of the test blocks, accessing pins in the group for the associate sub-flow under control of the test block.

14. The method of claim 13 , wherein:
each test block accesses pins in only one flow domain.

15. The method of claim 13 , wherein:
at least one core is mapped to multiple tester sites.

16. The method of claim 6 , wherein:
each of the identified groups of pins comprises a flow domain.

17. The method of claim 6 , wherein:
the method further comprises, at a first time, receiving input specifying the portion of the test blocks for concurrent execution; and
at a second time, receiving user input specifying sequential execution of the plurality of test blocks; and
in response to the user input, sequentially executing the plurality of test blocks.

18. The method of claim 6 , wherein:
the at least one semiconductor component comprises a plurality of like semiconductor components, each of the like semiconductor components comprising a like plurality of cores, the plurality of cores on each of the plurality of devices comprising cores of a plurality of types; and
the tester sites are partitioned into a plurality of site regions, each site region being associated with a type of core such that each tester site within the group is associated with a core of the type on a device of the group of devices.

19. The method of claim 18 , further comprising:
automatically

Assignees

• King Jason D
• Pye Richard
• Stimson Randall B
• Shirk Steven R
• Teradyne Inc

Inventors

• King Jason D
• Pye Richard
• Stimson Randall B
• Shirk Steven R

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G01R31/2834

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/01 Primary

  Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station (testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12) · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic