Synchronization of internal oscillators of components sharing a communications bus

Patent metadata

Field	Value
Publication number	US-10128783-B2
Application number	US-201615169540-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	May 31, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A drive circuit includes an internal oscillator and a pre-drive controller coupled to the internal oscillator. The pre-drive controller can have a switch control output configured to be coupled to a switch input. The pre-drive controller can receive switch control data, receive a clock signal, receive a synchronization signal, synchronize the internal oscillator based on the clock signal and the synchronization signal, and generate a pulse modulated switching signal at the switch control output based on the switch control data and the internal oscillator.

First claim

What is claimed is:

1. A drive circuit, comprising:
an internal oscillator configured to provide an internal oscillating signal; and
a pre-drive controller coupled to the internal oscillator, the pre-drive controller comprising a plurality of switch control outputs each configured to be coupled to a switch, wherein the pre-drive controller is configured to:
receive, on a first input of a data bus, digital switch control data from a motor controller, the digital switch control data comprising duty cycle information for a multiphase motor,
receive, on a clock signal input of the data bus, a clock signal,
receive, on a second input of the data bus, a synchronization signal,
upon receiving the synchronization signal on the second input, synchronize the internal oscillator based on a first timing difference between a first edge and a second edge of the clock signal, or based on a second timing difference and a third timing difference, the second timing difference being a timing difference between a third edge of the clock signal and an edge of the synchronization signal, and the third timing difference being a timing difference between a fourth edge of the clock signal and the edge of the synchronization signal, and

generate a pulse modulated switching signal for each phase of the multiphase motor at a corresponding one of the plurality of switch control outputs based on the digital switch control data and the internal oscillating signal.

2. The drive circuit of claim 1 , wherein the clock signal is a clock signal from a serial peripheral interface (SPI) bus and wherein the synchronization signal is a chip select signal from the SPI bus.

3. The drive circuit of claim 1 , further comprising a plurality of switch driver circuits each having an input coupled to a corresponding one of the plurality of switch control outputs.

4. The drive circuit of claim 1 , wherein the pre-drive controller comprises a synchronization circuit configured to synchronize the internal oscillator by:
calculating a delay between a rising edge or falling edge of the synchronization signal and a falling edge or rising edge of the clock signal, respectively; and
adjusting a phase of the internal oscillator by offsetting the internal oscillating signal by the delay.

5. The drive circuit of claim 1 , wherein the pre-drive controller is a first controller and the internal oscillator is a first internal oscillator; and the drive circuit further comprises a second controller configured according to the first controller and a second internal oscillator coupled to the second controller, wherein, after synchronizing the second internal oscillator, a phase of the second internal oscillator is substantially the same as a phase of the first internal oscillator.

6. The drive circuit of claim 1 , wherein the pulse modulated switching signal is a pulse width modulated switching signal.

7. The drive circuit of claim 1 , further comprising a plurality of switches, wherein each switch of the plurality of switches is coupled to a corresponding one of the plurality of switch control outputs.

8. The drive circuit of claim 7 , wherein each switch switches power to a phase of the multiphase motor.

9. The drive circuit of claim 1 , wherein the pre-drive controller is further configured to:
receive analog feedback from a switch receiving the pulse modulated switching signal;
digitize the feedback; and
provide the digitized feedback to the motor controller.

10. The drive circuit of claim 1 , wherein the pre-drive controller is located on a substrate of an integrated circuit.

11. The drive circuit of claim 1 , wherein the synchronization signal is a second synchronization signal, wherein the pre-drive controller is further configured to receive, prior to receiving the second synchronization signal on the second input, a first synchronization signal on the first input, the first synchronization signal notifying the pre-drive controller that the second synchronization signal is a triggering signal to trigger synchronization.

12. A method, comprising:
receiving, at a data input of a pre-drive controller, digital switch control data from a motor controller, the digital switch control data comprising duty cycle information for a first phase of a multiphase motor;
receiving, at the pre-drive controller, a clock signal;
receiving, at the pre-drive controller, a synchronization signal;
upon receiving the synchronization signal, synchronizing an internal oscillator of the pre-drive controller that provides an internal oscillating signal, based on a first timing difference between a first edge and a second edge of the clock signal or based on a second timing difference and a third timing difference, the second timing difference being a timing difference between a third edge of the clock signal and an edge of the synchronization signal, and the third timing difference being a timing difference between a fourth edge of the clock signal and the edge of the synchronization signal;
generating a pulse modulated switching signal for the first phase of the multiphase motor based on the digital switch control data and the internal oscillating signal; and
providing the pulse modulated switching signal to a switch.

13. The method of claim 12 , wherein the clock signal is a clock signal from a serial peripheral interface (SPI) bus, wherein the synchronization signal is a chip select signal from the SPI bus, and wherein the digital switch control data is received over the SPI bus.

14. The method of claim 12 , wherein providing the pulse modulated switching signal comprises driving a switching input of the switch with the pulse modulated switching signal.

15. The method of claim 12 , wherein synchronizing the internal oscillator comprises:
calculating a delay between a rising edge or falling edge of the synchronization signal and a falling edge or rising edge of the clock signal, respectively; and
adjusting a phase of the internal oscillating signal provided by the internal oscillator by offsetting the internal oscillating signal by the delay.

16. The method of claim 12 , wherein the pulse modulated switching signal is a pulse width modulated switching signal.

17. The method of claim 12 , further comprising:
receiving feedback from the switch;
digitizing the feedback; and
providing the digitized feedback to the motor controller.

18. The method of claim 12 , wherein the pre-drive controller is a first pre-drive controller, the method further comprising:
receiving, at a second pre-drive controller, the digital switch control data from the motor controller for the first phase of the multiphase motor;
receiving, at the second pre-drive controller, the clock signal;
receiving, at the second pre-drive controller, the synchronization signal;
upon receiving the synchronization signal, synchronizing an internal oscillator of the second pre-drive controller based on a fourth timing difference in the second pre-drive controller between a fifth edge and a sixth edge of the clock signal or based on a fifth timing difference and a sixth timing difference, the fifth timing difference being a timing difference between a seventh edge of the clock signal and a second edge of the synchronization signal, and the sixth timing difference being a timing difference between an eighth edge of the clock signal and the second edge of the synchronization signal;
generating a second pulse modulated switching signal for the first phase of the multiphase motor based on the digital switch control data received at the second pre-drive contro

Assignees

• Infineon Technologies Ag

Inventors

• Bogus Matthias
• Heiling Christian
• Anastasov Ljudmil
• Koeppl Benno

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• H02P6/10 Primary

  Arrangements for controlling torque ripple, e.g. providing reduced torque ripple · CPC title

• H03K17/18

  Modifications for indicating state of switch · CPC title