Correcting duty cycle and compensating for active clock edge shift

Patent metadata

Field	Value
Publication number	US-10892744-B2
Application number	US-201715714012-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 25, 2017
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.

First claim

What is claimed is:

1. A system comprising:
at least one control circuit logically configured to receive duty cycle correction control signals and logically configured to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, and wherein the at least one control circuit is configured to maintain a constant delay between at least one adjustment circuit and at least one correction circuit;
the at least one adjustment circuit logically coupled to the at least one control circuit and logically configured to change a duty cycle value of an input clock signal in response to receiving the at least one first adjustment signal on a first adjustment input of the at least one adjustment circuit and the at least one second adjustment signal on a second adjustment input of the at least one adjustment circuit, wherein changing a duty cycle value comprises introducing a first delay in the input clock signal, resulting in a second clock signal;
the at least one correction circuit logically coupled to the at least one control circuit, logically coupled to the at least one adjustment circuit, and logically configured to compensate for a shift of an active clock edge of the input clock signal in response to receiving the at least one first correction signal on a first correction input of the at least one correction circuit and the at least one second correction signal on a second correction input of the at least one correction circuit, wherein compensating for a shift of an active clock edge comprises introducing a second delay in the second clock signal, resulting in a corrected output clock signal;
wherein the value of the second delay is based on the constant delay, the first delay, and the shift;
wherein the difference between the input clock signal and the corrected output clock signal is the constant delay;
wherein one of the set of the at least one adjustment circuit and the at least one correction circuit is logically configured to transmit the corrected output clock signal, in response to the at least one adjustment circuit receiving the at least one first adjustment signal and the at least one second adjustment signal and in response to the at least one correction circuit receiving the at least one first correction signal and the at least one second correction signal.

2. The system of claim 1 wherein the at least one adjustment circuit comprises:
an adjustment clock input, an adjustment voltage supply input, the first adjustment input, the second adjustment input, an adjustment ground input, and an adjustment clock output;
an adjustment inverter circuit logically coupled to the adjustment clock input and logically coupled to the adjustment clock output;
an adjustment p-type transistor logically coupled to the first adjustment input, logically coupled to the adjustment inverter circuit, and logically coupled to the adjustment clock output;
a first pull-up p-type transistor logically coupled to the adjustment clock input, electrically coupled to the adjustment voltage supply input, and logically coupled to the adjustment p-type transistor;
an adjustment n-type transistor logically coupled to the second adjustment input, logically coupled to the adjustment inverter circuit, logically coupled to the adjustment p-type transistor, and logically coupled to the adjustment clock output; and
a first pull-down n-type transistor logically coupled to the adjustment clock input, electrically coupled to the adjustment ground input, and logically coupled to the adjustment n- type transistor.

3. The system of claim 2 wherein the at least one correction circuit comprises:
a correction clock input, a correction voltage supply input, the first correction input, the second correction input, a correction ground input, and a correction clock output;
a correction inverter circuit logically coupled to the correction clock input and logically coupled to the correction clock output;
a correction p-type transistor logically coupled to the first correction input, logically coupled to the correction inverter circuit, and logically coupled to the correction clock output;
a second pull-up p-type transistor logically coupled to the correction clock input, electrically coupled to the correction voltage supply input, and logically coupled to the correction p-type transistor;
a correction n-type transistor logically coupled to the second correction input, logically coupled to the correction inverter circuit, logically coupled to the correction p-type transistor, and logically coupled to the correction clock output; and
a second pull-down n-type transistor logically coupled to the correction clock input, electrically coupled to the correction ground input, and logically coupled to the correction n-type transistor.

4. The system of claim 3
wherein the adjustment clock input of a first adjustment circuit among the at least one adjustment circuit is logically configured to receive the input clock signal,
wherein the adjustment clock input of a second adjustment circuit among the at least one adjustment circuit is logically coupled to the adjustment clock output of the first adjustment circuit,
wherein the correction clock input of a first correction circuit among the at least one correction circuit is logically coupled to the adjustment clock output of the second adjustment circuit,
wherein the correction clock input of a second correction circuit among the at least one correction circuit is logically coupled to the correction clock output of the first correction circuit, and
wherein the correction clock output of the second correction circuit is logically configured to transmit the corrected output clock signal.

5. The system of claim 3
wherein the adjustment clock input of a first adjustment circuit among the at least one adjustment circuit is logically configured to receive the input clock signal,
wherein the correction clock input of a first correction circuit among the at least one correction circuit is logically coupled to the adjustment clock output of the first adjustment circuit,
wherein the adjustment clock input of a second adjustment circuit among the at least one adjustment circuit is logically coupled to the correction clock output of the first correction circuit,
wherein the correction clock input of a second correction circuit among the at least one correction circuit is logically coupled to the adjustment clock output of the second adjustment circuit, and
wherein the correction clock output of the second correction circuit is logically configured to transmit the corrected output clock signal.

6. The system of claim 3
wherein the adjustment clock input of a first adjustment circuit among the at least one adjustment circuit is logically configured to receive the input clock signal,
wherein the correction clock input of a first correction circuit among the at least one correction circuit is logically coupled to the adjustment clock output of the first adjustment circuit,
wherein the correction clock input of a second correction circuit among the at least one correction circuit is logically coupled to the correction clock output of the first correction circuit,
wherein the adjustment clock input of a second adjustment circuit among the at least one adjustment circuit is logically coupled to the correction clock output of the second correction circuit, and
wherein the adjustment clock output of the second adjustment circuit is logically configured to transmit the corrected output clock signal.

7. The system of claim 3
wherein the correction clock input of a first correction circuit among the at least one correction circuit is logically configured to receive the

Assignees

• IBM

Inventors

• Koch Michael
• Ringe Matthias
• Arp Andreas
• Cilek Fatih

Classifications

• H03K2005/00065

  by current control, e.g. by parallel current control transistors · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K2005/00071

  by adding capacitance as a load · CPC title

• H03K21/08

  Output circuits · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title