Duty cycle detection and correction circuit in an integrated circuit

Patent metadata

Field	Value
Publication number	US-9520867-B2
Application number	US-201514724226-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Dec 31, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A clock generating circuit includes a clock generator, a first clock tree, a second clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal. The first clock tree includes a driver cell configured to generate a first output clock signal based on the first clock signal and a set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The second clock tree includes a driver cell configured to generate a third output clock signal based on the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.

First claim

What is claimed is:

1. A clock generating circuit, the circuit comprising:
a clock generator configured to generate a first clock signal and a second clock signal, the first clock signal and the second clock signal having a predetermined phase difference;
a first clock tree comprising a driver cell configured to generate a first output clock signal based on the first clock signal and a set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals;
a second clock tree comprising a driver cell configured to generate a third output clock signal based on the first clock signal and the set of control signals; and
a duty cycle correction circuit configured to receive the first output clock signal and the second output clock signal and to generate the set of control signals based on the first output clock signal and the second output clock signal.

2. The clock generating circuit of claim 1 , wherein the duty cycle correction circuit comprises:
a first latch device configured to sample the first output clock signal based on the second output clock signal; and
a second latch device configured to sample the first output clock signal based on an inverse of the second output clock signal.

3. The clock generating circuit of claim 2 , wherein the duty cycle correction circuit further comprises:
a control logic circuit configured to receive a first logic output signal from the first latch device and a second logic output signal from the second latch device and, based on the first logic output signal and the second logic output signal, generate the set of control signals.

4. The clock generating circuit of claim 3 , wherein the control logic circuit is configured to generate the set of control signals by increasing a binary code of the set of control signals corresponding to a pull-down adjusting circuit of the driver cell of the first clock tree responsive to the first logic output signal being a logic ‘1’ and the second logic output signal being a logic ‘1’ when an inverse control signal of the set of control signals is a logic ‘0’.

5. The clock generating circuit of claim 3 , wherein the logic control circuit is configured to generate the set of control signals by decreasing a binary code of the set of control signals corresponding to a pull-down adjusting circuit of the driver cell of the first clock tree responsive to a first logic output signal being a logic ‘0’ and the second logic output signal being a logic ‘0’ when an inverse control signal of the set of control signals is a logic ‘1’.

6. The clock generating circuit of claim 3 , wherein the control logic circuit is configured to generate the control signal by decreasing a binary code of the set of control signals corresponding to a pull-up adjusting circuit of the driver cell of the first clock tree responsive to the first logic output signal being a logic ‘0’ and the second logic output signal being a logic ‘0’ when an inverse control signal of the set of control signals is a logic ‘0’.

7. The clock generating circuit of claim 3 , wherein the logic control circuit is configured to generate the control signal by increasing a binary code of the set of control signals corresponding to a pull-up adjusting circuit of the driver cell of the first clock tree responsive to the first logic output signal being a logic ‘1’ and the second logic output signal being a logic ‘1’ when an inverse control signal of the set of control signals is a logic ‘1’.

8. The clock generating circuit of claim 3 , wherein the control logic circuit is configured to set an inverse control signal of the set of control signals from a logic ‘0’ to a logic ‘1’ responsive to a binary code of the set of control signals corresponding to a pull-up adjusting circuit of the driver cell of the first clock tree and a binary code of the set of control signals corresponding to a pull-down adjusting circuit of the driver cell of the first clock tree being “11” or “00”.

9. The clock generating circuit of claim 1 , wherein the driver cell of the first clock tree comprises:
a first delay cell and a second delay cell, wherein the first delay cell is a buffer cell configured to delay an input clock signal being either the first clock signal or second clock signal, and the second delay cell is an inverter cell configured to invert the input clock signal;
a multiplexer configured to select the delayed input clock signal or the inverted signal of the input clock signal in response to an inverse control signal; and
a driving circuit comprising a pull-up adjusting circuit and a pull-down adjusting circuit, the driving circuit coupled to receive the clock signal selected by the multiplexer, the pull-up adjusting circuit and the pull-down adjusting circuit adjustable based on the set of control signals.

10. The clock generating circuit of claim 1 , wherein the first clock signal and the second clock signal are a pair of inverted signals.

11. The clock generating circuit of claim 1 , wherein the duty cycle correction circuit is further configured to generate the set of control signals independently of the third output clock signal.

12. A method of generating clock signals, comprising:
generating by a first driver cell a first output clock signal based on a first clock signal and a set of control signals;
generating by the first driver cell a second output clock signal based on a second clock signal and the set of control signals, the first clock signal and the second clock signal having a predetermined phase difference;
determining a duty cycle of the first output clock signal based on the first output clock signal and the second output clock signal;
adjusting the set of control signals according to the duty cycle of the first output clock signal; and
generating by a second driver cell a third output clock signal based on the first clock signal and the set of control signals.

13. The method of claim 12 , wherein determining the duty cycle of the first output clock signal based on the first output clock signal and the second output clock signal comprises:
sampling the first output clock signal based on the second output clock signal and generating a first logic output signal; and
sampling the first output clock signal based on an inverse of the second output clock signal and generating a second logic output signal.

14. The method of claim 13 , wherein adjusting the set of control signals is performed based on the first logic output signal and the second logic output signal.

15. The method of claim 14 , further comprising:
maintaining the set of control signals when the first logic output signal and the second logic output signal have different logic values.

16. The method of claim 14 , wherein adjusting the set of control signals comprises:
increasing or decreasing binary codes of the set of control signals corresponding to a pull-up adjusting circuit or a pull-down adjusting circuit of the first driver cell when the first and second logic output signals have a same logic value.

17. The method of claim 14 , wherein adjusting the set of control signals comprises:
setting a control signal of the set of control signals in response to the first logic output signal and the second logic output signal, the control signal of the set of control signals corresponding to causing the first driver cell to selectively buffer or invert the first output clock.

18. The method of claim 13 , wherein the predetermined phase difference is a 180-degree phase difference.

19. The method

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Mu-Shan

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title