Resistive random access memory device

Patent metadata

Field	Value
Publication number	US-10886465-B2
Application number	US-201815908601-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Feb 28, 2018
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

First claim

What is claimed is:

1. A memory cell, comprising:
a substrate;
a first contact feature disposed above the substrate;
a first barrier layer completely surrounding the first contact feature;
a resistive material layer disposed above the first contact feature;
a second contact feature disposed above the resistive material layer;
a second barrier layer completely surrounding the second contact feature;
a source/drain feature of a transistor, the source/drain feature being formed in the substrate; and
a conductive plug disposed directly below the first contact feature and the resistive material layer, and electrically coupling the first contact feature to the source/drain feature.

2. The memory cell of claim 1 , wherein the resistive material layer presents a variable resistance value.

3. The memory cell of claim 1 , wherein the at least one of the first and second contact features is partially embedded in a low-k dielectric layer.

4. The memory cell of claim 3 , wherein the first barrier layer comprises a first portion disposed between the low-k dielectric layer and the first contact feature.

5. The memory cell of claim 4 , wherein the first portion of the first barrier layer extends along a top boundary, a lower boundary and sidewalls of the first contact feature.

6. The memory cell of claim 3 , wherein the first barrier layer comprises a second portion disposed above the low-k dielectric layer.

7. The memory cell of claim 6 , wherein the second portion of the first barrier layer is formed as a thin film that fully overlays an upper boundary of the first contact feature.

8. The memory cell of claim 1 , wherein the first and second contact features each comprises a copper interconnection structure.

9. The memory cell of claim 1 , further comprising:
a transistor coupled to the first contact feature.

10. The memory cell of claim 1 , wherein the first and second barrier layers are formed of tantalum nitride and tantalum.

11. A memory cell, comprising:
a substrate;
a first contact feature at least partially embedded in a first dielectric layer formed above the substrate;
a first barrier layer, completely surrounding the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer;
a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer;
a second contact feature embedded in a second dielectric layer above the first dielectric layer; and
a second barrier layer completely surrounding the second contact feature;
a source/drain feature of a transistor, the source/drain feature being formed in the substrate; and
a conductive plug disposed directly below the first contact feature and the resistive material layer, and electrically coupling the first contact feature to the source/drain feature.

12. The memory cell of claim 11 , wherein the resistive material layer presents a variable resistance value.

13. The memory cell of claim 11 , wherein the first and second dielectric layers are each formed of a low-k dielectric material.

14. The memory cell of claim 11 , wherein the first portion of the first barrier layer extends along a lower boundary and sidewalls of the first contact feature.

15. The memory cell of claim 11 , the second portion of the first barrier layer fully overlays an upper boundary of the first contact feature.

16. The memory cell of claim 11 , wherein the first and second contact features each comprises a copper interconnection structure.

17. The memory cell of claim 11 , further comprising:
a transistor coupled to the first contact feature.

18. The memory cell of claim 11 , wherein the first and second barrier layers are formed of tantalum nitride and tantalum.

19. A memory cell, comprising:
a substrate
a first contact feature at least partially embedded in a first dielectric layer formed above the substrate;
a first barrier layer, completely surrounding the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer;
a first capping material disposed above the first barrier layer;
a resistive material layer disposed above the first capping material;
a second capping material disposed above the resistive material layer;
a second contact feature disposed above the second capping material and embedded in a second dielectric layer above the first dielectric layer; and
a second barrier layer completely surrounding the second contact feature a source/drain feature of a transistor, the source/drain feature being formed in the substrate; and
a conductive plug disposed directly below the first contact feature and the resistive material layer, and electrically coupling the first contact feature to the source/drain feature.

20. The memory cell of claim 19 , wherein:
the resistive material layer presents a variable resistance value; and
the first and second dielectric layers are each formed of a low-k dielectric material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Huei-Tsz
• Wang Po-Shu
• Wang Wei-Ming

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title