Semiconductor device with well region and protection region electrically connected by connection region

Patent metadata

Field	Value
Publication number	US-10886401-B2
Application number	US-201616305170-A
Country	US
Kind code	B2
Filing date	May 30, 2016
Priority date	May 30, 2016
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

A semiconductor device includes: a substrate; a drift region formed on a main surface of the substrate; a well region formed in a main surface of the drift region; a source region formed in the well region; a gate groove formed from the main surface of the drift region in a perpendicular direction while being in contact with the source region, the well region, and the drift region; a drain region formed in the main surface of the drift region; a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween; a protection region formed on a surface of the gate insulating film facing the drain region; and a connection region formed in contact with the well region and the protection region.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a drift region of a first conductivity type formed on a first main surface of the substrate and having a higher impurity concentration than the substrate;
a well region of a second conductivity type extending in the drift region from a second main surface of the drift region in a direction perpendicular to the second main surface, the second main surface being opposite from a first main surface of the drift region in contact with the substrate;
a source region of the first conductivity type extending in the well region from the second main surface in the perpendicular direction;
a gate groove formed from the second main surface in the perpendicular direction and extending in contact with the source region, the well region in a direction parallel to the second main surface, and the drift region;
a drain region of the first conductivity type formed away from the well region in the drift region and extending from the second main surface in the perpendicular direction;
a gate insulating film formed on a surface of the gate groove;
a gate electrode formed on a surface of the gate insulating film;
a source electrode electrically connected to the source region and the well region;
a drain electrode electrically connected to the drain region;
a protection region of the second conductivity type formed in the drift region, on a surface of the gate insulating film facing the drain region; and
a connection region of the second conductivity type formed in the drift region while being in contact with the well region and the protection region, wherein
the well region and the protection region are electrically connected to each other by the connection region.

2. The semiconductor device according to claim 1 , wherein the connection region is formed in contact with a bottom surface of the gate insulating film facing the substrate.

3. The semiconductor device according to claim 1 , wherein at least part of the connection region is formed inside the substrate.

4. The semiconductor device according to claim 1 , wherein at least part of the protection region is formed inside the substrate.

5. The semiconductor device according to claim 1 , wherein the connection region has a higher impurity concentration than the well region.

6. The semiconductor device according to claim 1 , wherein the connection region is in contact with the source electrode.

7. The semiconductor device according to claim 6 , wherein the connection region is in contact with the source electrode at a position deeper than the second main surface.

8. The semiconductor device according to claim 1 , further comprising a plurality of the protection regions, wherein adjacent protection regions and the drift region sandwiched by the adjacent protection regions are fully depleted at a predetermined voltage.

9. The semiconductor device according to claim 1 , wherein the substrate is made of an insulator or a semi-insulator.

10. The semiconductor device according to claim 1 , wherein the drift region and the substrate are formed of the same material.

11. The semiconductor device according to claim 1 , wherein the protection region is in contact with an entire end surface of the gate groove facing the drain region.

12. The semiconductor device according to claim 1 , wherein
a depth of the protection region is equal to a depth of the gate groove, and
a width of the protection region is equal to a width of the gate groove.

13. The semiconductor device according to claim 1 , wherein the connection region is formed from the second main surface of the drift region to a depth shallower than a depth of the gate groove.

Assignees

• Nissan Motor

Inventors

• Ni Wei
• Hayashi Tetsuya
• Hayami Yasuaki
• Tanaka Ryota

Classifications

• H10D64/511

  for IGFETs · CPC title

• H10D84/0156

  Manufacturing their doped wells · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D30/64 Primary

  Double-diffused metal-oxide semiconductor [DMOS] FETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title